EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 100

• Manufacturer Part Number: EZ80190AZ050EG
• Description: IC WEBSERVER 50MHZ XTEMP 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050EG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3865; EZ80190AZ050EG

PS006614-1208
SPI Status Register
Table 40. SPI Status Register
SPI Transmit Shift Register
Bit
Reset
CPU Access
Note: R = Read Only.
Bit
Position
7
SPIF
6
WCOL
5
4
MODF
[3:0]
The SPI Status Read Only register, listed in
using the serial peripheral interface. Reading the SPIx_SR register clears bits 7, 6, and 4 to
a logical 0.
The SPI Transmit Shift register (SPIx_TSR) is used by the SPI master to transmit data
onto the SPI serial bus to the slave device. A write to the SPIx_TSR register places data
directly into the shift register for transmission. A write to this register within an SPI device
configured as a master initiates transmission of a byte of the data loaded into the register.
After completing this transmission, the SPIF status bit (SPIx_SR[7]) is set to 1 in both the
master and slave devices.
The SPI Transmit Shift Write Only registers share the same address space as the SPI
Receive Buffer Read Only registers.
Value Description
0
1
0
1
0
0
1
0000b Reserved—must be 0.
The SPI data transfer is not finished.
The SPI data transfer is finished. If enabled, an interrupt is
generated. This bit flag is cleared to 0 by a read of the
SPIx_SR register.
An SPI write collision is not detected.
An SPI write collision is detected. This bit flag is cleared to 0
by a read of the SPIx_SR registers.
Reserved—must be 0.
A mode fault (multimaster conflict) is not detected.
A mode fault (multimaster conflict) is detected. This bit flag is
cleared to 0 by a read of the SPIx_SR register.
R
7
0
R
6
0
R
5
0
(SPI0_SR = B7h, SPI1_SR = BBh)
Table
R
4
0
40, returns the status of data transmitted
R
3
0
R
2
1
Product Specification
Serial Peripheral Interface
R
1
0
R
0
0
eZ80190
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