EZ80190AZ050EG Zilog, EZ80190AZ050EG Datasheet - Page 86
EZ80190AZ050EG
Manufacturer Part Number
EZ80190AZ050EG
Description
IC WEBSERVER 50MHZ XTEMP 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80190AZ050SG.pdf
(221 pages)
Specifications of EZ80190AZ050EG
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Processor Series
EZ80190x
Core
eZ80
Data Bus Width
8 bit
Program Memory Type
ROMLess
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
32
Number Of Timers
6
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3865
EZ80190AZ050EG
EZ80190AZ050EG
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PS006614-1208
UART FIFO Control Registers
Table 31. UART FIFO Control Registers
Bit
Reset
CPU Access
Note: W = Write Only.
Bit
Position
[7:6]
TRIG
[5:3]
1
CLRTXF
2
CLRRXF
0
FIFOEN
These registers, listed in
and enable or disable the FIFO. The UARTx_FCTL registers share the same I/O addresses
as the UARTx_IIR registers.
Value
00
01
10
11
000b
0
1
0
1
0
1
Description
The receive FIFO trigger level is set to 1. A receive data
interrupt is generated when there is 1 byte in the FIFO. This bit
is valid only if the FIFO is enabled.
The receive FIFO trigger level set to 4. The receive data
interrupt is generated when there are 4 bytes in the FIFO. This
bit is valid only if the FIFO is enabled.
The receive FIFO trigger level set to 8. The receive data
interrupt is generated when there are 8 bytes in the FIFO. This
bit is valid only if the FIFO is enabled.
The receive FIFO trigger level set to 14. The receive data
interrupt is generated when there are 14 bytes in the FIFO.
This bit is valid only if the FIFO is enabled.
Reserved—must be 000b.
This bit produces no effect.
This bit clears the transmit FIFO and resets the transmit FIFO
pointer. This bit is valid only if the FIFO is enabled.
This bit produces no effect.
This bit clears the receive FIFO, clears the receive error FIFO,
and resets the receive FIFO pointer. This bit is valid only if the
FIFO is enabled.
The transmit and receive FIFOs are disabled. The transmit and
receive buffers are only one byte deep.
The transmit and receive FIFOs are enabled.
W
7
0
Table
W
6
0
31, are used to monitor trigger levels, clear FIFO pointers,
W
5
0
(UART0_FCTL = C2h, UART1_FCTL = D2h)
W
4
0
Universal Asynchronous Receiver/Transmitter
W
3
0
W
2
0
Product Specification
W
1
0
W
0
1
eZ80190
76
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