MPC8360EZUAJDGA Freescale Semiconductor, MPC8360EZUAJDGA Datasheet - Page 94

IC MPU POWERQUICC II PRO 740TBGA

MPC8360EZUAJDGA

Manufacturer Part Number
MPC8360EZUAJDGA
Description
IC MPU POWERQUICC II PRO 740TBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8360EZUAJDGA

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
533MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
740-TBGA
Processor Series
MPC8xxx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
MPC8360E-RDK
Maximum Clock Frequency
533 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
I/o Voltage
1.8 V, 2.5 V, 3.3 V
Minimum Operating Temperature
0 C
For Use With
MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8360EZUAJDGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Clocking
The RCWL[CEVCOD] denotes the QUICC Engine Block PLL VCO internal frequency as shown in
Table
The QUICC Engine block VCO frequency is derived from the following equations:
94
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
75.
ce_clk = (primary clock input × CEPMF) ÷ (1 + CEPDF)
QE VCO Frequency = ce_clk × VCO divider × (1 + CEPDF)
The VCO divider (RCWL[CEVCOD]) must be set properly so that the
QUICC Engine block VCO frequency is in the range of 600–1400 MHz.
The QUICC Engine block frequency is not restricted by the CSB and core
frequencies. The CSB, core, and QUICC Engine block frequencies should
be selected according to the performance requirements.
Table 74. QUICC Engine Block PLL Multiplication Factors (continued)
Note:
1. Reserved modes are not listed.
RCWL[CEPMF] RCWL[CEPDF]
01011
01101
01111
10001
10011
10101
10111
11001
11011
11101
Table 75. QUICC Engine Block PLL VCO Divider
RCWL[CEVCOD]
1
1
1
1
1
1
1
1
1
1
00
01
10
11
NOTE
Multiplication Factor = RCWL[CEPMF]/
VCO Divider
Reserved
(1 + RCWL[CEPDF])
QUICC Engine PLL
4
8
2
× 10.5
× 11.5
× 12.5
× 13.5
× 14.5
× 5.5
× 6.5
× 7.5
× 8.5
× 9.5
Freescale Semiconductor

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