MPC8360EZUAJDGA Freescale Semiconductor, MPC8360EZUAJDGA Datasheet - Page 40

• Manufacturer Part Number: MPC8360EZUAJDGA
• Description: IC MPU POWERQUICC II PRO 740TBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8360EZUAJDGA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 533MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 740-TBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC8360E-RDK
• Maximum Clock Frequency: 533 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 1.8 V, 2.5 V, 3.3 V
• Minimum Operating Temperature: 0 C
• For Use With: MPC8360EA-MDS-PB - KIT APPLICATION DEV 8360 SYSTEMMPC8360E-RDK - BOARD REFERENCE DESIGN FOR MPC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

UCC Ethernet Controller: Three-Speed Ethernet, MII Management
8.3.2
Table 37
40
At recommended operating conditions with LV
Input low voltage
Input current
MDC frequency
MDC period
MDC clock pulse width high
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
MDC fall time
Notes:
1. The symbols used for timing specifications follow the pattern of t
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz
3. This parameter is dependent on the ce_clk speed (that is, for a ce_clk of 200 MHz, the delay is 90 ns and for a ce_clk of
inputs and t
data timing (MD) for the time t
Also, t
(V) relative to the t
convention is used with the appropriate letter: R (rise) or F (fall).
and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum
frequency is 1.7 MHz).
300 MHz, the delay is 63 ns).
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
Table 36. MII Management DC Electrical Characteristics When Powered at 3.3 V (continued)
MDRDVKH
Parameter/Condition
provides the MII management AC timing specifications.
Parameter
MII Management AC Electrical Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state
MDC
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
Table 37. MII Management AC Timing Specifications
MDC
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time.
Symbol
DD
V
I
IN
IL
is 3.3 V ± 10%.
t
t
t
t
Symbol
MDTKHDX
MDTKHDV
MDRDVKH
MDRDXKH
t
t
t
f
t
MDCH
MDCR
MDHF
MDC
MDC
1
0 V ≤ V
Conditions
IN
—
Min
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
32
10
10
—
—
—
—
—
≤ OV
0
DD
Typ
400
2.5
—
—
—
—
—
—
Min
—
—
MDKHDX
Max
110
10
10
—
—
—
—
—
—
symbolizes management
Freescale Semiconductor
Max
0.80
±10
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
Notes
Unit
μA
—
—
—
—
—
—
for
V
2
3