MPC8315ECVRAGDA Freescale Semiconductor, MPC8315ECVRAGDA Datasheet - Page 98

• Manufacturer Part Number: MPC8315ECVRAGDA
• Description: MPU POWERQUICC II PRO 620-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8315ECVRAGDA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocking
Table 72
(see
24.1
The system PLL is controlled by the RCWL[SPMF] parameter.
encodings for the system PLL.
98
e300 core frequency ( core_clk )
Coherent system bus frequency ( csb_clk )
DDR1/2 memory bus frequency (MCK)
Local bus frequency (LCLK n )
PCI input frequency (SYS_CLKIN or PCI_CLK)
Notes:
1. The SYS_CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen such that the resulting csb_clk ,
2. The DDR data rate is 2x the DDR memory bus frequency.
3. The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
MCK, LCLK[0:1], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
the csb_clk frequency (depending on RCWL[LBIUCM]).
Table
provides the operating frequencies for the TEPBGA II under recommended operating conditions
System PLL Configuration
2).
eTSEC1
eTSEC2
Security Core, I2C, SAP, TPR
USB DR
PCI and DMA complex
PCIe
Serial ATA
If RCWL[DDRCM] and RCWL[LBCM] are both cleared, the system PLL
VCO frequency = (CSB frequency) × (System PLL VCO Divider).
If either RCWL[DDRCM] or RCWL[LBCM] are set, the system PLL VCO
frequency = 2 × (CSB frequency) × (System PLL VCO Divider).
The VCO divider needs to be set properly so that the System PLL VCO
frequency is in the range of 450–750 MHz.
MPC8315E PowerQUICC
Unit
3
Characteristic
Table 72. Operating Frequencies for TEPBGA II
2
Table 71. Configurable Clock Units
™
1
II Pro Processor Hardware Specifications, Rev. 0
Default Frequency
csb_clk
csb_clk
csb_clk
csb_clk
csb_clk
csb_clk
csb_clk
NOTE
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk
Off, csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Table 73
Max Operating Frequency
shows the multiplication factor
Options
24-66
400
133
133
66
Freescale Semiconductor
MHz
MHz
MHz
MHz
MHz
Unit