MPC8315ECVRAGDA Freescale Semiconductor, MPC8315ECVRAGDA Datasheet

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... The MPC8315E incorporates the e300c3 (MPC603e-based) core, which includes 16 Kbytes of L1 instruction and data caches, on-chip memory management units (MMUs), and floating-point support. In addition to the e300 core, the SoC © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: MPC8315EEC ™ II Pro Processor 1 ...

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... HS PHY Note: The MPC8315 do not include a security engine. Figure 1. MPC8315E Block Diagram ™ II Pro Processor Hardware Specifications, Rev. 0 Enhanced DDR1/DDR2 Local Bus, TDM Controller SPI eTSEC SATA SATA RGMII, (R)MII RGMII, (R)MII PHY PHY RTBI, SGMII RTBI, SGMII Freescale Semiconductor eTSEC ...

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... HMAC with either algorithm • Random number generator (RNG) — Combines a True Random Number Generator (TRNG) and a NIST-approved Pseudo-Random Number Generator (PRNG) (as described in Annex C of FIPS140-2 and ANSI X9.62). MPC8315E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 MPC8315E Features 3 ...

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... Up to 128 time slots, where each slot can be programmed to be active or inactive • 16-bit word widths • The TDM Transmitter Sync Signal (TFS), Transmitter Clock Signal (TCK) and Receiver Clock • Signal (RCK) can be configured as either input or output MPC8315E PowerQUICC 4 ™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor ...

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... Dedicated descriptor based DMA engine per interface with separate read and write channels 2.9 Dual Serial ATA (SATA) Controllers The SATA controllers have the following features: • Designed to comply with Serial ATA Rev 2.5 Specification MPC8315E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 MPC8315E Features 5 ...

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... Provides power management when the device is used in both PCI host and agent modes • PCI Power Management 1.2 D0, D1, D2, D3hot, and D3cold states • PME generation in PCI agent mode, PME detection in PCI host mode MPC8315E PowerQUICC 6 ™ II Pro Processor Hardware Specifications, Rev. 0 Freescale Semiconductor ...

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... Both may exist in the same system. The local bus can operate MHz. The system timers include the following features: periodic interrupt timer, real time clock, software watchdog timer, and two general-purpose timer blocks. MPC8315E PowerQUICC Freescale Semiconductor 2 C, DUART, Enhanced Local Bus Controller ™ ...

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... II Pro Processor Hardware Specifications, Rev Max Value Unit Notes –0.3 to 1.26 V — –0.3 to 1.26 V — –0.3 to 2.7 V — –0.3 to 1.9 V — –0 –0 –0.3 to 3.6 –0.3 to 1.26 V — –0.3 to 3.6 V — –0.3 to 1.26 V — –0.3 to 1.26 V — –0.3 to 3.6 V — Freescale Semiconductor ...

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... SerDes internal digital power SerDes internal digital power SerDes I/O digital power SerDes I/O digital power SerDes analog power for PLL SerDes analog power for PLL Dedicated 3.3 V analog power for USB PLL MPC8315E PowerQUICC Freescale Semiconductor 1 (continued) Symbol MV –0.3 to (GVDD + 0.3) IN MVREF – ...

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... V Switched Off — V Switched On — V Switched Off — V Switched On — V Switched Off — V Switched Off — V Switched Switched Switched Off 2 V Switched Off 2 V Switched Off 2 V Switched Off 2 V Switched Off — V Switched On — V — — Freescale Semiconductor ...

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... Figure 2. Overshoot/Undershoot Voltage for GVDD/NVDD/LVDD 3.1.3 Output Driver Characteristics Table 3 provides information on the characteristics of the output driver strengths. The values are preliminary estimates. Driver Type Local bus interface utilities signals PCI signals MPC8315E PowerQUICC Freescale Semiconductor Recommended Symbol ;maximum temperature is specified with T A GND ...

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... Power sequence for switchable power supplies Figure 3. Power-Up Sequencing ™ II Pro Processor Hardware Specifications, Rev. 0 Supply Voltage 18 GVDD = 2 GVDD = 1 NVDD = 3 NVDD = 3 LVDD = 3 2.5 V Figure 3. Once all the power μ s, this requirement is for ESD Switchable I/O Voltage Switchable Core Voltage (VDD) 0 Freescale Semiconductor ...

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... The SATA power supplies VDD33PLL and VDD33ANA should go high after NVDD3_OFF supply and go low before NVDD3_OFF supply. The NVDD3_OFF voltage levels should not drop below the VDD33PLL, VDD33ANA voltages at any time. MPC8315E PowerQUICC Freescale Semiconductor CAUTION Figure 4 when implemented along with low power D3 ...

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... II Pro Processor Hardware Specifications, Rev. 0 NVDD3_OFF Time Table . 4 1,3 1,2 Maximum Unit 1.646 W 1.665 W 1.690 W = 105•C, and an artificial smoker C, and an artificial smoker j Table 5. SATA_VDD, XCOREVDD VDD33PLL, VDD1IO, , XPADVDD, VDD33ANA VDD1ANA SDAVDD (3.3V) (1.0V) (1.0V) — — — — — — Freescale Semiconductor Unit W W ...

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... GHz — x1lane SATA two 3.0 GHz — ports Other I/O — — 5 Clock Input Timing This section provides the clock input DC and AC electrical characteristics for the MPC8315E. MPC8315E PowerQUICC Freescale Semiconductor LVDD1_OFF/ LVDD2 LVDD2_ON _ON (3.3 V) (3.3V) (3.3V) — — ...

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... Min Max Unit 2.4 NVDD + 0.3 V -0.3 0.4 V μA — ±10 μA — ±40 μA — ±10 μA — ±10 μA — ±10 μA — ±40 μA — ±10 Table 7 provides the clock Max Unit Notes 66 MHz 41 1 ±150 Freescale Semiconductor ...

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... CFG_SYS_CLKIN_DIV) with respect to negation of PORESET when the device is in PCI agent mode Input hold time for POR configuration signals with respect to negation of HRESET Time for the device to turn off POR configuration signals with respect to the assertion of HRESET MPC8315E PowerQUICC Freescale Semiconductor Symbol Condition V — — ...

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... PCI_SYNC_IN Max Unit Notes μs 100 — μs 100 — μs 100 — μs 100 — μs 100 — Max Unit Notes 1.9 V 0.51 × GVDD V MVREF + 0.04 V GVDD + 0.3 V — MVREF – 0.125 V — μA 9.9 4 — mA — Freescale Semiconductor ...

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... Peak-to-peak noise on MVREF may not exceed ±2% of the DC value not applied directly to the device the supply to which far end signal termination is made and is expected equal to MVREF. This rail should track variations in the DC level of MVREF. 4. Output leakage is measured with all outputs disabled MPC8315E PowerQUICC Freescale Semiconductor Symbol Min I 13.4 OL ≤ ...

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... II Pro Processor Hardware Specifications, Rev. 0 Min Max Unit Notes — 0 GVDD/2, V (peak-to-peak) = 0.2 V. OUT OUT REF Max Unit Note μA 500 1 Max Unit Notes MVREF – 0.45 V — V Max Unit MVREF – 0.51 V — V Freescale Semiconductor 1 1 — — Notes ...

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... CISKEW Figure 6 shows the DDR SDRAM input AC timing for the tolerated MDQS to MDQ skew (t MCK[n] MCK[n] MDQS[n] MDQ[x] MPC8315E PowerQUICC Freescale Semiconductor Symbol Min t CISKEW 266 MHz –875 200 MHz –1250 )) where T is the clock period and abs(t CISKEW ...

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... II Pro Processor Hardware Specifications, Rev. 0 Max Unit Notes — — ns — — ns — — ns — — 0 — — ps — — –0.5 × t – 0.6 + 0.6 ns MCK 0.6 ns memory clock MCK describes the DDR timing DDKHMH can be modified through DDKHMH follows the DDKHMP Freescale Semiconductor for ...

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... MDQS MDQS Figure 8 shows the DDR and DDR2 SDRAM output timing diagram. MCK MCK ADDR/CMD Write A0 MDQS[n] MDQ[x] Figure 8. DDR and DDR2 SDRAM Output Timing Diagram MPC8315E PowerQUICC Freescale Semiconductor t MCK t = 0.6 ns DDKHMH(max –0.6 ns DDKHMH(min) Figure 7. Timing Diagram for t DDKHMH t MCK ...

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... Figure 9. DDR AC Test Load Table 22. DUART AC Timing Specifications Parameter > 1,000,000 ™ II Pro Processor Hardware Specifications, Rev. 0 GVDD Ω Symbol Min Max V 2.1 NVDD + 0 –0.3 0 NVDD – 0.2 — — 0 — ± Value Unit Notes 256 baud — baud 1 16 — 2 Freescale Semiconductor Unit μA ...

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... Output high voltage Output low voltage Input high voltage Input low voltage Input high current Input low current Note: 1. The symbol this case, represents the LV IN MPC8315E PowerQUICC Freescale Semiconductor Section 9.3, “Ethernet Management Symbol Conditions LVDD — — –4.0 mA LVDD = Min ...

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... LVDD + 0.3 V – 0.3 0.40 SS 1.7 LVDD + 0.3 –0.3 0.70 — 15 –15 — Table 1 and Table 2. Min Typ Max — 400 — — 40 — 35 — 1.0 — 4.0 1.0 — 4.0 symbolizes MII transmit MTKHDX Freescale Semiconductor Unit μA μA Unit for ...

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... For example, the subscript of t MRX used with the appropriate letter: R (rise (fall). Figure 11 provides the AC test load for eTSEC. Output MPC8315E PowerQUICC Freescale Semiconductor t MTX t t MTXH MTXF t MTKHDX Figure 10 ...

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... RMII(RM) reference (X) clock. For rise and fall RMX ™ II Pro Processor Hardware Specifications, Rev MRXR t MRDXKH Table 27 provides the Min Typ Max — 20 — 35 — — 10 1.0 — 4.0 1.0 — 4.0 for outputs. For example, t RMTKHDX Freescale Semiconductor Unit ...

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... Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. For example, the subscript of t times, the latter convention is used with the appropriate letter: R (rise (fall). Figure 14 provides the AC test load. Output MPC8315E PowerQUICC Freescale Semiconductor t RMX t t RMXH RMXF ...

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... RTBI (T) receive (RX) clock. Note also that the RGT ™ II Pro Processor Hardware Specifications, Rev RMXR t RMRDXKH Min Typ Max –0.6 — 0.6 1.0 — 2.6 7.2 8.0 8 — — 0.75 — — 0.75 — 8.0 — 47 — the lowest speed transitioned RGT Freescale Semiconductor Unit ...

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... The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics for MDIO and MDC are provided in Table 30. MII Management DC Electrical Characteristics Powered at 3.3 V Parameter Supply voltage (3.3 V) Output high voltage Output low voltage Input high voltage Input low voltage MPC8315E PowerQUICC Freescale Semiconductor t RGTH t SKRGT TXD[8:5] TXD[3:0] TXD[7:4] TXD[9] TXD[4] ...

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... Min Max Unit μA — 40 μA –600 — Table 1 and Table 2. Typ Max Unit Notes 2.5 — MHz 2 400 — ns — — — ns — — 170 ns 3 — — ns — — — ns — — — — — symbolizes MDKHDX Freescale Semiconductor ...

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... Input high voltage Input low voltage Input current 9.4.2 1588 Timer AC Specifications Table 33 provides the 1588 timer AC specifications. Parameter Timer clock cycle time Input setup to timer clock Input hold from timer clock MPC8315E PowerQUICC Freescale Semiconductor t MDC t t MDCF MDCH t MDDVKH t MDDXKH t ...

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... AC-Coupled capacitor. Each TX Figure 49. as long as such termination does not violate SD_REF_CLK and SD_REF_CLK ™ II Pro Processor Hardware Specifications, Rev. 0 Min Max Unit — — — Min Typical Max Units Notes - — — 100 ps –50 — Freescale Semiconductor Notes 2 — — — ...

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... OS 5. The |V | value shown in the Typ column is based on the condition of XCOREVDD 500 mV), SerDes transmitter is terminated with 100-Ω differential load between TX[n] and TX[n]. OS MPC8315E PowerQUICC Freescale Semiconductor . Symbol Min Typ 0.95 VOH — VOL ...

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... TXm TXn 50 Ω 50 Ω 50 Ω 50 Ω TXn Symbol Min Typ XCOREVDD 0.95 1.0 — N/A V 100 — RX_DIFFp-p 175 — ™ II Pro Processor Hardware Specifications, Rev Ω Receiver 50 Ω 50 Ω Transmitter 50 Ω Max Unit Notes 1.05 V — — 1 1200 Freescale Semiconductor ...

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... At recommended operating conditions with XCOREVDD = 1.0V ± 5%. Parameter Deterministic Jitter Total Jitter Unit Interval V fall time (80%-20 rise time (20%-80%) OD Notes: 1. Each UI is 800 ps ± 100 ppm. MPC8315E PowerQUICC Freescale Semiconductor Ethernet: Three-Speed Ethernet, MII Management Symbol Min Typ VLOS 30 — 65 — V — — CM_ACp-p ...

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... JDR 0.55 — JSIN 0.1 — JT 0.65 — BER — — UI 799.92 800 C 5 — TX ™ II Pro Processor Hardware Specifications, Rev. 0 Max Unit Notes — UI p-p 1 — UI p-p 1 — UI p-p 1 — UI p-p 1 -12 10 — 800. 200 nF 3 Freescale Semiconductor ...

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... Figure 20. SGMII Receiver Input Compliance Mask Figure 21. SGMII AC Test/Measurement Load 10 USB 10.1 USB Dual-Role Controllers This section provides the AC and DC electrical specifications for the USB-ULPI interface. MPC8315E PowerQUICC Freescale Semiconductor 0.275 0.4 0.6 Time (UI) ™ II Pro Processor Hardware Specifications, Rev. 0 USB 1 0 ...

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... II Pro Processor Hardware Specifications, Rev. 0 Min Max 2 LVDD + 0.3 IH –0.3 0 — ±5 IN LVDD – 0.2 — OH — 0.2 OL Table 1 and Table 2. Min Max Unit 15 — — — ns — — ns symbolizes USB timing USIXKH NVDD Ω Freescale Semiconductor Unit V V μ Notes for USKHOX ...

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... Table 42 provides the USB clock input (USB_CLK_IN) AC timing specifications. Table 42. USB_CLK_IN AC Timing Specifications Parameter/Condition Frequency range Clock frequency tolerance Reference clock duty cycle Total input jitter/Time interval error MPC8315E PowerQUICC Freescale Semiconductor t USIVKH t t USKHOX USKHOV Figure 23. USB Signals Symbol Min V 2 ...

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... LBIVKH t LBIXKH t LBOTOT1 t LBOTOT2 t LBOTOT3 ™ II Pro Processor Hardware Specifications, Rev. 0 Min Max NVDD – 0.2 — OH — 0 NVDD + 0.3 IH –0.3 0.8 IL — ±5 IN Min Max Unit 15 — — ns 1.0 — ns 1.5 — — ns 2.5 — ns Freescale Semiconductor Unit μA Notes ...

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... For active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. Figure 24 provides the AC test load for the local bus. Output MPC8315E PowerQUICC Freescale Semiconductor 1 Symbol t LBKHOV t ...

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... UPM Mode Output Signals: LCS[0:3]/LBS[0:1]/LGPL[0:5] Figure 26. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV MPC8315E PowerQUICC 44 t LBIVKH t LBKHOV t LBKHOZ t LBKHOV t LBOTOT t LBKHOZ t LBKHOV t LBIVKH t LBKHOZ t LBKHOV ™ II Pro Processor Hardware Specifications, Rev LBIXKH t LBIVKH t LBIXKH t LBIXKH t LBIXKH t LBIXKH t LBIVKH Freescale Semiconductor ...

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... DC electrical characteristics for the IEEE 1149.1 (JTAG) interface. Table 45. JTAG Interface DC Electrical Characteristics Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage MPC8315E PowerQUICC Freescale Semiconductor t LBKHOZ t LBKHOV t LBIVKH t t LBKHOZ ...

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... II Pro Processor Hardware Specifications, Rev. 0 Table 46 through Figure 32. 1 Min Max Unit Notes 0 33.3 MHz 30 — — — — 4 — — 10 — — 2 — the midpoint of the signal in question. TCLK Table 28). symbolizes JTAG JTDVKH clock JTG Freescale Semiconductor — — — — ...

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... TRST timing diagram. TRST Figure 31 provides the boundary-scan timing diagram. JTAG External Clock Boundary Data Inputs t JTKLDX Boundary Data Outputs Boundary Output Data Valid Data Outputs MPC8315E PowerQUICC Freescale Semiconductor = 50 Ω JTKHKL t JTG VM = Midpoint Voltage (NVDD/ TRST VM = Midpoint Voltage (NVDD/2) Figure 30 ...

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... Input Data Valid Output Data Valid 2 C interface of the MPC8315E. Min Max Unit 0.7 × NVDD NVDD + 0.3 V 0.3 × NVDD –0.3 V 0.2 × NVDD 0 V 0.8 × NVDD NVDD + 0 0.1 × C 250 — Freescale Semiconductor Notes — — 1 — — ...

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... Data hold time: Fall time of both SDA and SCL signals Setup time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) MPC8315E PowerQUICC Freescale Semiconductor Electrical Characteristics (continued) Symbol interface ...

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... II Pro Processor Hardware Specifications, Rev Symbol Min Max 0.2 × NVDD V — symbolizes I I2DVKH clock reference (K) going to I2C of the SCL signal) to bridge the IHmin ) of the SCL signal. I2CL NVDD Ω I2CF t I2CR t I2PVKH P S Freescale Semiconductor Unit V for C timing I2PVKH ...

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... For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification. 4. Input timings are measured at the pin. MPC8315E PowerQUICC Freescale Semiconductor Symbol Test Condition ≥ V ...

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... PCI timing (PC) with respect to PCRHFV = 50 Ω Ω Figure 35. PCI AC Test Load t PCIVKH t PCIXKH ™ II Pro Processor Hardware Specifications, Rev. 0 Max Unit Notes — — — for outputs. For example, t PCIVKH NVDD/2 Freescale Semiconductor ...

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... The Differential Output Voltage (or Swing) of the transmitter, V the two complimentary output voltages: V negative. 3. Differential Input Voltage, V The Differential Input Voltage (or Swing) of the receiver, V two complimentary input voltages Differential Peak Voltage, V MPC8315E PowerQUICC Freescale Semiconductor t PCKHOV (or Differential Output Swing): OD – V The V TXn TXn ...

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... B| Volts. DIFFp DIFFp |(A - B)| Volts, which is twice of differential DIFFp-p DIFFp = 2*|V TX-DIFFp-p OD Figure example for differential waveform. cm Differential Swing Differential Peak Voltage, V Differential Peak-Peak Voltage, V DIFFpp ™ II Pro Processor Hardware Specifications, Rev cm_out DIFFp = 2*V (not shown) DIFFp Freescale Semiconductor = (V TXn ...

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... XCOREVSS DC exceeds the maximum input current limitations, then it must be AC-coupled off-chip. • The input amplitude requirement — This requirement is described in detail in the following sections. MPC8315E PowerQUICC Freescale Semiconductor is 500 mV in one phase and –500 mV in the other 500 mV. The peak-to-peak differential voltage (V DIFFp ™ ...

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... AC-coupled externally. For the best noise performance, the reference of the clock could be DC MPC8315E PowerQUICC 56 50 Ω Input Amp 50 Ω Figure 40 shows the SerDes reference clock input requirement Figure 41 shows the SerDes reference clock input ™ II Pro Processor Hardware Specifications, Rev. 0 Figure 42 shows Freescale Semiconductor ...

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... Interfacing With Other Differential Signaling Levels With on-chip termination to XCOREVSS, the differential reference clocks inputs are HCSL (High-Speed Current Steering Logic) compatible DC-coupled. MPC8315E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 High-Speed Serial Interfaces (HSSI) Vmax < 800 mV 100 mV < Vcm < 400 mV Vmin > ...

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... They might also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits. The system designer is recommended ...

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... R2 = 25Ω. Please consult clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip. MPC8315E PowerQUICC Freescale Semiconductor SD_REF_CLK 100 Ω differential PWB trace SD_REF_CLK ™ ...

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... SD_REF_CLK Total 50 Ω. Assume clock driver’s output impedance is about 16 Ω. SD_REF_CLK 100 Ω differential PWB trace SD_REF_CLK Ω 50 ™ II Pro Processor Hardware Specifications, Rev. 0 MPC8315E 50 Ω SerDes Refer. CLK Receiver 50 Ω MPC8315E 50 Ω SerDes Refer. CLK Receiver 50 Ω Freescale Semiconductor ...

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... IH 0 –200 IL SDn_REF_CL K minus Figure 47. Differential Measurement Points for Rise and Fall Time SDn_REF_CLK SDn_REF_CLK Figure 48. Single-Ended Measurement Points for Rise and Fall Time Matching MPC8315E PowerQUICC Freescale Semiconductor Symbol Rise Edge Rate Fall Edge Rate V +200 Rise-Fall Matching Figure 47. ...

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... DC Requirements for PCI Express SD_REF_CLK and SD_REF_CLK For more information, see Section 15.2, “SerDes Reference MPC8315E PowerQUICC 62 RXn TXn 50 Ω 50 Ω TXn RXn Characteristics” Clocks.” ™ II Pro Processor Hardware Specifications, Rev. 0 SD_REF_CLK” Clocks” 50 Ω Receiver 50 Ω Freescale Semiconductor ...

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... Unit interval Differential peak-to-peak V TX-DIFFp-p output voltage De-Emphasized V TX-DE-RATIO differential output voltage (ratio) Minimum TX eye width T TX-EYE MPC8315E PowerQUICC Freescale Semiconductor Comments UI Each UI is 400 ps ± 300 ppm. UI does not account for Spread Spectrum Clock dictated variations 2*|V TX-DIFFp-p TX- TX-D- Ratio of the V ...

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... The total current the Transmitter can provide when shorted to its ground ™ II Pro Processor Hardware Specifications, Rev. 0 Min Typical Max Units — — 0. 0.125 — — — — — 100 — — — — 600 mV — — 3.6 V — — Freescale Semiconductor Notes — ...

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... Transmitter DC Z TX-DC impedance Lane-to-Lane output skew L TX-SKEW AC coupling capacitor C MPC8315E PowerQUICC Freescale Semiconductor Comments Minimum time a Transmitter must be in Electrical Idle Utilized by the Receiver to start looking for an Electrical Idle Exit after successfully receiving an Electrical Idle ordered set After sending an Electrical ...

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... II Pro Processor Hardware Specifications, Rev. 0 Min Typical Max Units Notes 0 — Figure 52 and measured over Figure 50.) = 0.30 UI for the TX-JITTER-MAX median is less than half of the total Figure 52). Note that the series capacitors, Figure 52 for both V and V TX-D+ TX-D- Freescale Semiconductor 7 . ...

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... Table 55. Differential Receiver (RX) Input Specifications Parameter Symbol Unit interval Differential peak-to-peak V RX-DIFFp-p output voltage Minimum receiver eye T RX-EYE width MPC8315E PowerQUICC Freescale Semiconductor = 0 mV TX-DIFF [Transition Bit 800 mV TX-DIFFp-p-MIN [De-emphasized Bit] 566 mV (3 dB) >= V >= 505 mV (4 dB) TX-DIFFp-p-MIN 0 – 0.3 UI(J TX-TOTAL-MAX ...

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... II Pro Processor Hardware Specifications, Rev. 0 Min Typical Max Units — — 0 — — 150 mV 15 — — — — dB Ω 80 100 120 Ω Ω 200 k — — — 175 mV — — Freescale Semiconductor Notes — — ...

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... RX component designer should provide additional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in adequate combination of system simulations and the return loss measured looking into the RX package MPC8315E PowerQUICC Freescale Semiconductor Comments Skew across all lanes on a Link. This includes variation in the length of SKP ordered set (e ...

Page 70

... D+ and D– not being exactly matched in length at the package pin boundary. MPC8315E PowerQUICC 70 NOTE Figure 52). Note that the series capacitors > 175 mV RX-DIFFp-p-MIN 0 RX-EYE-MIN NOTE ™ II Pro Processor Hardware Specifications, Rev PEACCTX RX-DIFF (D+ D– Crossing Point) Figure 52. Freescale Semiconductor ...

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... Input Low Voltage V CLK_INLo Reference clock rise and fall time t CLK_RISE t CLK_FALL Reference clock duty cycle t CLK_DUTY MPC8315E PowerQUICC Freescale Semiconductor Conditions — — — — / 20% to 80% of nominal amplitude measured at 1.6V ™ II Pro Processor Hardware Specifications, Rev. 0 Serial ATA (SATA) Table 56 ...

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... Conditions peak to peak jitter at refClk input T L Symbol Min Typical — 1.5 3.0 — T 666.4333 UI 333.3333 ™ II Pro Processor Hardware Specifications, Rev. 0 Min Typical Max Unit — — 100 Max Units Notes — Gbps — ps Freescale Semiconductor Notes — — — ...

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... DC electrical characteristics for the timers pins, including TIN, TOUT, TGATE, and RTC_CLK. Table 60. Timers DC Electrical Characteristics Characteristic Output high voltage Output low voltage Output low voltage Input high voltage Input low voltage Input current MPC8315E PowerQUICC Freescale Semiconductor Symbol Min V 50 SATA_OOBDETE 75 T — SATA_UIOOB T — ...

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... 8 3 — — ≤ V ≤ NVDD ™ II Pro Processor Hardware Specifications, Rev Symbol Min Unit TIWID ns to ensure proper operation. NVDD/2 Min Max Unit 2.4 — V — 0.5 V — 0.4 V 2.1 NVDD + 0.3 V –0.3 0.8 V μA — ± 5 Freescale Semiconductor ...

Page 75

... DC electrical characteristics for the external interrupt pins. Characteristic Input high voltage Input low voltage Input current Output high voltage Output low voltage Output low voltage MPC8315E PowerQUICC Freescale Semiconductor = 50 Ω Figure 55. GPIO AC Test Load Table 64. IPIC DC Electrical Characteristics Symbol Condition V — ...

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... PIWID Min Max 2.1 NVDD + 0.3 –0.3 0.8 — ±5 2.4 — — 0.5 — 0 Symbol Min Max t — 6 NIKHOV t 0.5 NIKHOX t — 8.5 NEKHOV t 2 — NEKHOX t 6 — NIIVKH t 0 — NIIXKH Freescale Semiconductor Unit ns Unit V V μ Unit ...

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... Output Signals: SPIMISO (See Note) Note: The clock edge is selectable on SPI. Figure 57. SPI AC Timing in Slave Mode (External Clock) Diagram MPC8315E PowerQUICC Freescale Semiconductor Table 67. SPI AC Timing Specifications (first two letters of functional block)(signal)(state)(reference)(state) for outputs. For example Ω Figure 56 ...

Page 78

... DM_LOW t DMIVKH t DMRDIXKH ™ II Pro Processor Hardware Specifications, Rev. 0 Min Max Unit 2.4 — — 0.5 — 0.4 2.1 NVDD + 0.3 –0.3 0.8 μA — ± 5 Min Max Units 20.0 — ns 8.0 — ns 8.0 — ns 3.0 — ns 3.5 — ns Freescale Semiconductor ...

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... Use of the rising edge or falling edge as a reference is programmable. TDMxTCK and TDMxRCK are shown using the rising edge. Figure 51 shows the TDM receive signal timing. TDMxRCK t DMIVKH TDMxRD t DMIVKH TDMxRFS TDMxRFS (output) MPC8315E PowerQUICC Freescale Semiconductor Table 69. TDM AC Timing specifications Symbol t DMFSIXKH t DM_OUTAC t DMTKHOV t DMTKHOX t DM_OUTHI ...

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... MPC8315E PowerQUICC DM_HIGH DM_LOW t DMTKHOV t DM_OUTAC t DMFSKHOV t DMFSIXKH Figure 60. TDM Transmit Signals Section 23.1, “Package Parameters for the 29 mm × 620 1 mm 2.23 mm 96.5 Sn/3.5 Ag (VR package) 0.6 mm ™ II Pro Processor Hardware Specifications, Rev DM_OUTHI t DMTKHOX t DMFSKHOX for information Freescale Semiconductor ...

Page 81

... Datum A, the seating plane, is determined by the spherical crowns of the solder balls. Figure 61. Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II 23.3 Pinout Listings Table 70 provides the pin-out listing for the TEPBGA II package. MPC8315E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 Package and Pin Listings 81 ...

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... I/O GVDD — I/O GVDD — I/O GVDD — I/O GVDD — I/O GVDD — I/O GVDD — I/O GVDD — I/O GVDD — I/O GVDD — I/O GVDD — I/O GVDD — I/O GVDD — I/O GVDD — Freescale Semiconductor ...

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... MEMC_MA3 MEMC_MA4 MEMC_MA5 MEMC_MA6 MEMC_MA7 MEMC_MA8 MEMC_MA9 MEMC_MA10 MEMC_MA11 MEMC_MA12 MEMC_MA13 MEMC_MA14 MEMC_MWE MEMC_MRAS MEMC_MCAS MEMC_MCS[0] MEMC_MCS[1] MPC8315E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type AF5 AE18 AE20 AE10 AF6 AF17 AG21 AG9 AF7 AH16 AH15 AG15 AD15 AE15 AH14 ...

Page 84

... I/O NVDD3 — _OFF I/O NVDD3 — _OFF I/O NVDD3 — _OFF I/O NVDD3 — _OFF O NVDD3 — _OFF O NVDD3 — _OFF O NVDD3 — _OFF O NVDD3 — _OFF O NVDD3 — _OFF O NVDD3 — _OFF O NVDD3 — _OFF Freescale Semiconductor ...

Page 85

... UART_SOUT1/MSRCID0 (DDR ID)/LSRCID0 UART_SIN1/MSRCID1 (DDR ID)/LSRCID1 UART_CTS[1]/MSRCID2 (DDR ID)/LSRCID2 UART_RTS[1]/MSRCID3 (DDR ID)/LSRCID3 UART_SOUT2/MSRCID4 (DDR ID)/LSRCID4 UART_SIN2/MDVAL (DDR ID)/LDVAL UART_CTS[2] UART_RTS[2] IIC_SDA/CKSTOP_OUT IIC_SCL/CKSTOP_IN MPC8315E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type AH23 AH24 AG23 AD22 AF25 AG24 AF24 AE23 ...

Page 86

... I NVDD1 4 _ON O NVDD1 3 _ON I NVDD1 4 _ON I NVDD1 4 _ON I/O NVDD1 — _OFF I/O NVDD1 — _OFF I/O NVDD1 — _OFF I/O NVDD1 — _OFF I/O NVDD1 — _OFF I/O NVDD1 — _OFF I VDD1IO — I VDD1IO — I VDD1IO — Freescale Semiconductor ...

Page 87

... SATA_VSS VSSRESREF RESREF VDD33ANA VDD33PLL TEST_MODE QUIESCE HRESET PORESET SYS_XTAL_IN SYS_XTAL_OUT SYS_CLK_IN USB_XTAL_IN USB_XTAL_OUT USB_CLK_IN PCI_SYNC_OUT RTC_CLK MPC8315E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type T28 M25 P26 N25 R26 U26 V27 N27 U23 M27 V28 T26 T25 U27 T27 ...

Page 88

... NVDD2 — _OFF I/O NVDD2 — _OFF I/O NVDD2 — _OFF I/O NVDD2 — _OFF I/O NVDD2 — _OFF I/O NVDD2 — _OFF I/O NVDD2 — _OFF I/O NVDD2 — _OFF I/O NVDD2 — _OFF I/O NVDD2 — _OFF Freescale Semiconductor ...

Page 89

... PCI_C/BE[2] PCI_C/BE[3] PCI_PAR PCI_FRAME PCI_TRDY PCI_IRDY PCI_STOP PCI_DEVSEL PCI_IDSEL PCI_SERR PCI_PERR PCI_REQ0 PCI_REQ1/CPCI_HS_ES PCI_REQ2 PCI_GNT0 PCI_GNT1/CPCI_HS_LED PCI_GNT2/CPCI_HS_ENUM MPC8315E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type C24 A26 E20 A23 C22 E19 A22 C20 B21 D19 A19 A21 B19 H24 C27 ...

Page 90

... LVDD1 — _OFF O LVDD1 — _OFF I/O LVDD1 — _OFF O LVDD1 — _OFF I NVDD1 — _ON I/O NVDD1 9 _ON I/O NVDD1 2 _ON I/O LVDD2 — _ON I/O LVDD2 — _ON O LVDD2 — _ON I LVDD2 — _ON I LVDD2 — _ON Freescale Semiconductor ...

Page 91

... TSEC2_TXD[0]/CFG_RESET_SOURCE[3] TSEC2_TX_EN TSEC2_TX_ER TXA TXA RXA RXA TXB TXB RXB RXB SD_IMP_CAL_RX SD_REF_CLK SD_REF_CLK SD_PLL_TPD SD_IMP_CAL_TX SDAVDD SD_PLL_TPA_ANA SDAVSS USB_DP USB_DM MPC8315E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type C10 D10 A9 B9 A10 D8 D11 D12 B11 SGMII / PCIe PHY ...

Page 92

... NVDD4 — _OFF I/O NVDD4 — _OFF I/O NVDD4 — _OFF I/O NVDD4 — _OFF I/O NVDD4 — _OFF I/O NVDD4 — _OFF I/O NVDD1 — _OFF I/O NVDD1 — _OFF I/O NVDD1 — _OFF I/O NVDD1 — _OFF Freescale Semiconductor ...

Page 93

... NVDD3 _OFF NVDD4 _OFF VDD VDD1ANA VDD1IO VDDC MPC8315E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type Power and Ground Supplies Y11, Y12, Y14, Y15, Y17, AC8, AC11, AC14, AC17, AD6, AD9, AD17, AE8, AE13, AE19, AF10, AF15, AF21, AG2, AG3, ...

Page 94

... P24, R19, R20, R24 M24, N24, P19, P20, P25, P27, R25, R27, T24 P2, P10, R2, T1 R3, R10, U2, V2 P3, R9, U3 ™ II Pro Processor Hardware Specifications, Rev. 0 Power Notes Supply I — — I — — I — — I — — I — — I — — Freescale Semiconductor ...

Page 95

... ECC by default. To disable the ECC an external strong pull up resistor or a tri-state buffer is needed. 10.This pin should be connected to an external 2.7 K ±1% resistor connected to VSS. The resistor should be placed as close as possible to the input. MPC8315E PowerQUICC Freescale Semiconductor Package Pin Number Pin Type P5, P9, V3 ™ ...

Page 96

... II Pro Processor Hardware Specifications, Rev. 0 e300c3 core core_clk DDR MEMC_MCK Clock Divider MEMC_MCK /2 /n LCLK[0:1] LBC Clock Divider PCI_CLK/ PCI_SYNC_IN 1 PCI_SYNC_OUT 0 3 PCI_CLK_OUT[0:2] RTC RTC_CLK (32 kHz) SATA_CLK_IN PLL 50/75/100/ 125/150 MHz Freescale Semiconductor DDR Memory Device Local Bus Memory Device ...

Page 97

... In addition, some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk frequency. Those units have a default clock ratio that can be configured by a memory mapped register after the device comes out of reset. frequency. MPC8315E PowerQUICC Freescale Semiconductor Table 71 specifies which units have a configurable clock ™ II Pro Processor Hardware Specifications, Rev. 0 ...

Page 98

... Off, csb_clk, csb_clk/2, csb_clk/3 csb_clk Off, csb_clk csb_clk Off, csb_clk csb_clk Off, csb_clk, csb_clk/2, csb_clk NOTE ™ II Pro Processor Hardware Specifications, Rev. 0 Options Max Operating Frequency 400 133 133 66 24-66 Table 73 shows the multiplication factor Freescale Semiconductor Unit MHz MHz MHz MHz MHz ...

Page 99

... Reset High High High High 1 CFG_SYS_CLKIN_DIV doubles csb_clk if set low. 2 SYS_CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode. MPC8315E PowerQUICC Freescale Semiconductor Table 73. System PLL Multiplication Factors System PLL RCWL[SPMF] Multiplication Factor 0000 Reserved 0001 Reserved × 2 0010 × ...

Page 100

... Table 77. Suggested PLL Configurations Input Clock Frequency (MHz) CSB Frequency (MHz) Core Frequency (MHz) 33.33 25 ™ II Pro Processor Hardware Specifications, Rev VCO Divider PLL bypassed (PLL off, csb_clk clocks core directly) N Table 77 shows suggested PLL 133.33 266.66 100 250 Freescale Semiconductor ...

Page 101

... Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. MPC8315E PowerQUICC Freescale Semiconductor Table 77. Suggested PLL Configurations Input Clock Frequency (MHz) CSB Frequency (MHz) Core Frequency (MHz) 66.67 33 ...

Page 102

... The application board should be similar to the thermal test condition: the component is soldered to a board with internal planes. MPC8315E PowerQUICC 102 ) + P where P DD I/O I/O , can be obtained from the equation: J × × ™ II Pro Processor Hardware Specifications, Rev the power dissipation of the I/O drivers are possible Freescale Semiconductor ...

Page 103

... The heat sink choice is determined by the application environment (temperature, air flow, adjacent component power dissipation) and the physical space available. Because there is not a standard application environment, a standard heat sink is not required. MPC8315E PowerQUICC Freescale Semiconductor ) can be used to determine the junction temperature with a JT × θ ...

Page 104

... Natural Convection 0.5 m/s 1 m/s 2 m/s 603-224-9988 408-749-7601 ™ II Pro Processor Hardware Specifications, Rev × TEBGA II Junction-to-Ambient Thermal Resistance 14.4 11.4 10.1 8.9 12.3 9.3 8.5 7.9 12.5 9.7 8.5 7.7 10.9 8.5 7.5 7.1 Freescale Semiconductor ...

Page 105

... When attaching heat sinks to these devices, an interface material is required. The best method is to use thermal grease and a spring clip. The spring clip should connect to the printed circuit board, either to the board itself, to hooks soldered to the board plastic stiffener. Avoid attachment forces which would MPC8315E PowerQUICC Freescale Semiconductor 408-436-8770 800-522-6752 603-635-2800 ...

Page 106

... VDD through a low frequency filter scheme such as the following. MPC8315E PowerQUICC 106 + ( θ generates the core clock as a slave to the platform clock. The ) Section 24.2, “Core PLL Configuration.” level should always be equivalent to VDD, and preferably DD ™ II Pro Processor Hardware Specifications, Rev. 0 Section 24.1, “System PLL Freescale Semiconductor ...

Page 107

... They should also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo OSCON). MPC8315E PowerQUICC Freescale Semiconductor Figure 63, one to each of the AV 10 Ω 2.2 µF 2.2 µ ...

Page 108

... Figure 64. Driver Impedance Measurement × source source )) × 1/R . Solving for the output impedance gives source = V /R source 1 source ™ II Pro Processor Hardware Specifications, Rev. 0 Figure 64). The and R are designed to be close SW2 SW1 . Second, the output voltage is measured . The term source . Freescale Semiconductor = ...

Page 109

... Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier which may specify special application conditions. Each part number also contains a revision code which refers to the die mask revision number. MPC8315E PowerQUICC Freescale Semiconductor Table 80. Impedance Characteristics PCI Signals PCI Output Clocks ...

Page 110

... Table 83. Document Revision History Substantive Change(s) ™ II Pro Processor Hardware Specifications, Rev e300 Core DDR Revision 1 2 Frequency Frequency AD = 266 MHz D = 266 MHz Contact AF = 333 MHz local AG = 400 MHz Freescale sales office SVR (Rev 1.2) 0x80B4_0012 0x80B5_0012 0x80B6_0012 0x80B7_0012 Freescale Semiconductor A Level ...

Page 111

... THIS PAGE INTENTIONALLY LEFT BLANK MPC8315E PowerQUICC Freescale Semiconductor ™ II Pro Processor Hardware Specifications, Rev. 0 Document Revision History 111 ...

Page 112

... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...