MPC8315ECVRAGDA Freescale Semiconductor, MPC8315ECVRAGDA Datasheet - Page 46

• Manufacturer Part Number: MPC8315ECVRAGDA
• Description: MPU POWERQUICC II PRO 620-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8315ECVRAGDA

• Processor Type: MPC83xx PowerQUICC II Pro 32-Bit
• Speed: 400MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 620-PBGA
• Processor Series: MPC8xxx
• Core: e300
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

JTAG
12.2
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface.
provides the JTAG AC timing specifications as defined in
46
At recommended operating conditions (see
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
Input setup times:
Input hold times:
Valid times:
Output hold times:
JTAG external clock to output high impedance:
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of t
2. The symbols used for timing specifications herein follow the pattern of t
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to t
5. Non-JTAG signal output timing with respect to t
6. Guaranteed by design and characterization.
The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load (see
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
for inputs and t
device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t
reference (K) going to the high (H) state or setup time. Also, t
data input signals (D) went invalid (X) relative to the t
the clock reference symbol representation is based on three letters representing the clock of a particular functional. For rise
and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
JTAG AC Timing Specifications
(first two letters of functional block)(reference)(state)(signal)(state)
Table 46. JTAG AC Timing Specifications (Independent of SYS_CLKIN)
MPC8315E PowerQUICC
Parameter
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
Table
2)
TMS, TDI
TMS, TDI
TCLK
™
TCLK
II Pro Processor Hardware Specifications, Rev. 0
.
TDO
TDO
TDO
JTG
.
clock reference (K) going to the high (H) state. Note that, in general,
t
JTGR
Symbol
t
t
t
t
t
t
t
t
t
t
t
JTDXKH
JTDVKH
JTDXKH
JTKHKL
JTKLDV
JTKLOV
JTKLDX
JTKLOX
JTKLDZ
JTKLOZ
t
JTIVKH
JTIXKH
t
TRST
f
JTG
JTG
, t
JTGF
Figure 29
2
for outputs. For example, t
symbolizes JTAG timing (JT) with respect to the time
(first two letters of functional block)(signal)(state) (reference)(state)
TCLK
Min
30
15
25
10
10
0
0
4
4
2
2
2
2
2
2
through
to the midpoint of the signal in question.
Figure
Max
33.3
11
11
19
—
—
—
—
—
—
—
—
—
2
9
JTDVKH
Freescale Semiconductor
32.
1
symbolizes JTAG
MHz
Unit
Table
ns
ns
ns
ns
ns
ns
ns
ns
ns
JTG
Table 46
clock
28).
Notes
5, 6
—
—
—
—
3
4
4
5
5