MC68060RC50 Freescale Semiconductor, MC68060RC50 Datasheet - Page 102

• Manufacturer Part Number: MC68060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

have the V-bit and D-bit set, indicating that the line has valid entries that have not been writ-
ten to memory. A cache line changes states from valid or dirty to invalid if the execution of
the CINV or CPUSH instruction explicitly invalidates the cache line or if a snooped access
hits the cache line. Both caches should be explicitly cleared using the CINVA instruction
after a hardware reset of the processor since reset does not invalidate the cache lines.
Figure 5-4 illustrates the general flow of a caching operation. The caches use the physical
addresses, and to simplify the discussion, the discussion of the translation of logical to phys-
ical addresses is omitted.
address bits 10–4 are used to index into the cache and select 1 of 128 sets of cache lines.
Physical address bits 31–11 are used as a tag reference or to update the cache line tag
MOTOROLA
To determine if the physical address is already allocated in the cache, the lower physical
31
TAG DATA/TAG REFERENCE
PA31-PA11
PHYSICAL ADDRESS
TRANSLATED
Figure 5-4. Caching Operation
PA31–PA11
PHYSICAL
ADDRESS
11
10
SET SELECT
M68060 USER’S MANUAL
PHYSICAL
PA10–PA4
SET 128
SET 0
SET 1
INDEX
COMPARATOR
TAG
4
TAG
3 0
0
STATUS
STATUS
1
LINE 0
2
LW0 LW1 LW2 LW3
LW0 LW1 LW2 LW3
LINE 1
3
LINE 2
HIT 3
HIT 2
HIT 1
HIT 0
LINE 3
LOGICAL OR
MUX
LINE SELECT
INSTRUCTION
HIT
DATA OR
Caches
5-3