XC5VLX30-3FF324C Xilinx Inc, XC5VLX30-3FF324C Datasheet - Page 339
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-3FF324C
Manufacturer Part Number
XC5VLX30-3FF324C
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-3FF324C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IDELAYCTRL Timing
IDELAYCTRL Locations
Table 7-12
Table 7-12: IDELAYCTRL Switching Characteristics
As shown in
X-Ref Target - Figure 7-16
IDELAYCTRL modules exist in every I/O column in every clock region. An IDELAYCTRL
module calibrates all the IDELAY modules within its clock region. See
Clocks in Chapter 1
Figure 7-17
F
IDELAYCTRL_REF_PRECISION
T
IDELAYCTRLCO_RDY
IDELAYCTRL_REF
REFCLK
shows the IDELAYCTRL switching characteristics.
RST
RDY
illustrates the relative locations of the IDELAYCTRL modules.
Figure
Figure 7-16: Timing Relationship Between RST and RDY
Symbol
7-16, the Virtex-5 FPGA RST is an edge-triggered signal.
for the definition of a clock region.
www.xilinx.com
REFCLK frequency
REFCLK precision
Reset/Startup to Ready for IDELAYCTRL
Input/Output Delay Element (IODELAY)
T
Description
IDELAYCTRLCO_RDY
Global and Regional
ug190_7_11_041206
339
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