XC5VLX30-3FF324C Xilinx Inc, XC5VLX30-3FF324C Datasheet - Page 141
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-3FF324C
Manufacturer Part Number
XC5VLX30-3FF324C
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-3FF324C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Table 4-13: FIFO Capacity
Table 4-14: Comparison of Synchronous FIFO Implementations
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Synchronous FIFO Implementations
4k + 1 entries by 4 bits
2k + 1 entries by 9 bits
1k + 1 entries by 18 bits
512 + 1 entries by 36 bits
EN_SYN = TRUE, DO_REG = 0
EN_SYN = TRUE, DO_REG = 1
EN_SYN = FALSE, DO_REG = 1
RDCLK = WRCLK
18 Kb FIFO
Synchronous FIFO Implementations
Standard Mode
Table 4-14
timing differences.
X-Ref Target - Figure 4-16
8k + 1 entries by 4 bits
4k + 1 entries by 9 bits
2k + 1 entries by 18 bits
512 + 1 entries by 72 bits
1k + 1 entries by 36 bits
EN_SYN = FALSE
EN_SYN = TRUE
EN_SYN = TRUE
36 Kb FIFO
outlines varied implementations of synchronous FIFOs.
DO_REG = 0
DO_REG = 1
DO_REG = 1
No flag uncertainty
Faster clock-to-out signals, no
flag uncertainty
Faster clock-to-out signals.
Similar to a Virtex-4 FIFO.
Figure 4-16: Synchronous FIFO Data Timing Diagram
rdclk
rden
DO
DO
DO
Advantages
www.xilinx.com
4k + 2 entries by 4 bits
2k + 2 entries by 9 bits
1k + 2 entries by 18 bits
512 + 2 entries by 36 bits
18 Kb FIFO
Longer clock-to-out signals
Data Latency increased by one. Behaves
like a synchronous FIFO with an extra data
output pipeline register
Falling-edge flag uncertainty. Rising-edge
guaranteed on FULL and EMPTY
FWFT Mode
T
CKO
= 1.9ns
8k + 2 entries by 4 bits
4k + 2 entries by 9 bits
2k + 2 entries by 18 bits
1k + 2 entries by 36 bits
512 + 2 entries by 72 bits
Disadvantages
Built-in FIFO Support
Figure 4-16
36 Kb FIFO
ug190_c4_x1_071007
shows the
141
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