XC5VLX30-3FF324C Xilinx Inc, XC5VLX30-3FF324C Datasheet - Page 138
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-3FF324C
Manufacturer Part Number
XC5VLX30-3FF324C
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-3FF324C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 4: Block RAM
138
Block RAM Timing Model
Figure 4-15
This example takes the simplest paths on and off chip (these paths can vary greatly
depending on the design). This timing model demonstrates how and where the block
RAM timing parameters are used.
•
•
•
•
X-Ref Target - Figure 4-15
Synchronous
Write Enable
Set/Reset
NET = Varying interconnect delays
T
T
T
Address
IOPI
IOOP
BCCKO_O
Enable
Clock
Data
= Pad to I-output of IOB delay
= O-input of IOB to pad delay
illustrates the delay paths associated with the implementation of block RAM.
= BUFGCTRL delay
[T
[T
[T
[T
[T
[T
IOPI
IOPI
IOPI
IOPI
IOPI
IOPI
+ NET] + T
+ NET]
Figure 4-15: Block RAM Timing Model
+ NET] + T
+ NET] + T
[T
+ NET] + T
+ NET] + T
www.xilinx.com
BCCKO_O
BUFGCTRL
RCCK_ADDR
RCCK_WEN
RCCK_SSR
RCCK_EN
RDCK_DI
+ NET]
DI
ADDR
WE
EN
SSR
Block RAM
CLK
FPGA
DO
T
RCKO_DO
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
+ [NET + T
IOOP
ug190_4_14_022207
]
Data
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