XC5VLX30-3FF324C Xilinx Inc, XC5VLX30-3FF324C Datasheet - Page 159
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-3FF324C
Manufacturer Part Number
XC5VLX30-3FF324C
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-3FF324C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ECC Modes Overview
In the standard ECC mode (EN_ECC_READ = TRUE and EN_ECC_WRITE = TRUE), both
encoder and decoder are enabled. During write, 64-bit data and 8-bit ECC generated parity
are stored in the array. The external parity bits are ignored. During read, the 72-bit decoded
data and parity are read out.
The encoder and decoder can be accessed separately for external use in RAMB36SDP. To
use the encoder by itself, send the data in through the DI port and sample the ECCPARITY
output port. To use the decoder by itself, disable the encoder, write the data into the block
RAM and read the corrected data and status bits out of the block RAM. See
(RAMB36SDP)
To use the decoder in ECC decode-only mode, set EN_ECC_WRITE = FALSE and
EN_ECC_READ = TRUE.
The encoder can be used in two ways:
•
•
The functionality of the block RAM when using the ECC mode is described as follows:
•
•
•
•
•
To use the encoder in standard ECC mode, set (EN_ECC_WRITE = TRUE and
EN_ECC_READ = TRUE). In this mode, the DI setup time is smaller but the clock-to-
out for ECCPARITY is larger.
To use the encoder-only mode, set (EN_ECC_WRITE = TRUE and
EN_ECC_READ = FALSE). In this mode, the DI setup time is larger but the clock-to-
out for ECCPARITY is smaller.
The block RAM ports still have independent address, clocks, and enable inputs, but
one port is a dedicated write port, and the other is a dedicated read port (simple dual-
port).
DO represents the read data after correction.
DO stays valid until the next active read operation.
Simultaneous decoding and encoding, even with asynchronous clocks, is allowed, but
requires careful clock timing if read and write addresses are identical.
The NO_CHANGE or WRITE_FIRST modes of the normal block RAM operation are
not applicable to the ECC configuration.
Attributes.
www.xilinx.com
Built-in Error Correction
Block RAM
159
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