XC5VLX30-3FF324C Xilinx Inc, XC5VLX30-3FF324C Datasheet - Page 233
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-3FF324C
Manufacturer Part Number
XC5VLX30-3FF324C
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-3FF324C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Virtex-5 FPGA SelectIO Primitives
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IBUF and IBUFG
OBUF
The Xilinx software library includes an extensive list of primitives to support a variety of
I/O standards available in the Virtex-5 FPGA I/O primitives. The following are five
generic primitive names representing most of the available single-ended I/O standards.
•
•
•
•
•
These six generic primitive names represent most of the available differential I/O
standards:
•
•
•
•
•
•
Signals used as inputs to Virtex-5 devices must use an input buffer (IBUF). The generic
Virtex-5 FPGA IBUF primitive is shown in
X-Ref Target - Figure 6-18
The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is
used as a clock input. In the Xilinx software tools, an IBUFG is automatically placed at
clock input sites.
An output buffer (OBUF) must be used to drive signals from Virtex-5 devices to external
output pads. A generic Virtex-5 FPGA OBUF primitive is shown in
X-Ref Target - Figure 6-19
IBUF (input buffer)
IBUFG (clock input buffer)
OBUF (output buffer)
OBUFT (3-state output buffer)
IOBUF (input/output buffer)
IBUFDS (input buffer)
IBUFGDS (clock input buffer)
OBUFDS (output buffer)
OBUFTDS (3-state output buffer)
IOBUFDS (input/output buffer)
IBUFDS_DIFF_OUT (input buffer)
Figure 6-18: Input Buffer (IBUF/IBUFG) Primitives
Figure 6-19: Output Buffer (OBUF) Primitive
From device pad
From FPGA
I (Input)
www.xilinx.com
I (Input)
OBUF
IBUF/IBUFG
Figure
6-18.
Virtex-5 FPGA SelectIO Primitives
ug190_6_17_022806
O (Output)
to device pad
ug190_6_16_022806
O (Output)
into FPGA
Figure
6-19.
233
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