XC5VLX30-3FF324C Xilinx Inc, XC5VLX30-3FF324C Datasheet - Page 243
![IC FPGA VIRTEX-5 30K 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30-3FF324C
Manufacturer Part Number
XC5VLX30-3FF324C
Description
IC FPGA VIRTEX-5 30K 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30-3FF324C
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1179648
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
For Use With
HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
LVDCI (Low Voltage Digitally Controlled Impedance)
Table 6-8
standard.
Table 6-8: Allowed Attributes for the LVCMOS12 I/O Standard
Using these I/O buffers configures the outputs as controlled impedance drivers. The
receiver of LVDCI is identical to a LVCMOS receiver. Some I/O standards, such as LVTTL,
LVCMOS, etc., must have a drive impedance that matches the characteristic impedance of
the driven line. Virtex-5 devices provide a controlled impedance output driver to provide
series termination without external source termination resistors. The impedance is set by
the common external reference resistors, with resistance equal to the trace characteristic
impedance, Z
Sample circuits illustrating both unidirectional and bidirectional termination techniques
for a controlled impedance driver are shown in
standards supporting a controlled impedance driver are: LVDCI_15, LVDCI_18,
LVDCI_25, and LVDCI_33.
X-Ref Target - Figure 6-31
X-Ref Target - Figure 6-32
IOSTANDARD
DRIVE
SLEW
Figure 6-31: Controlled Impedance Driver with Unidirectional Termination
Figure 6-32: Controlled Impedance Driver with Bidirectional Termination
R 0 = R VRN = R VRP = Z 0
Attributes
details the allowed attributes that can be applied to the LVCMOS12 I/O
LVDCI
R 0 = R VRN = R VRP = Z 0
0
.
LVDCI
www.xilinx.com
IOB
IOB
IBUF/IBUFG
LVCMOS12
UNUSED
UNUSED
Specific Guidelines for I/O Supported Standards
Z 0
Z 0
Figure 6-31
OBUF/OBUFT
{FAST, SLOW}
LVCMOS12
Primitives
2, 4, 6, 8
IOB
IOB
R 0 = R VRN = R VRP = Z 0
and
LVDCI
Figure
LVDCI
ug190_6_28_022806
6-32. The DCI I/O
{FAST, SLOW}
LVCMOS12
ug190_6_29_022806
2, 4, 6, 8
IOBUF
243
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