EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 79
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Quantity
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Part Number:
EP4SGX360FH29C3N
Manufacturer:
Bussmann
Quantity:
40 000
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
ALTERA21
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Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Document Revision History
Document Revision History
Table 3–10. Document Revision History
February 2011 Altera Corporation
February 2011
March 2010
November 2009
June 2009
April 2009
March 2009
November 2008
May 2008
Date
Power Management
Version
Stratix IV memory block clock-enables allow you to control clocking of each memory
block to reduce AC power consumption. Use the read-enable signal to ensure that
read operations only occur when you need them to. If your design does not need
read-during-write, you can reduce your power consumption by de-asserting the
read-enable signal during write operations, or any period when no memory
operations occur.
The Quartus II software automatically places any unused memory blocks in
low-power mode to reduce static power.
Table 3–10
3.0
2.0
3.2
3.1
2.3
2.2
2.1
1.0
■
■
■
■
■
■
■
■
■
■
■
■
■
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Updated “Power-Up Conditions and Memory Initialization” on page 3–20
Initial release.
Updated the
sections.
Applied new template.
Minor text edits.
Updated the “Simple Dual-Port Mode”, “Same-Port Read-During-Write Mode”, and
“Mixed-Port Read-During-Write Mode” sections.
Updated Figure 3–14.
Minor text edits.
Updated Table 3–2.
Updated the “Simple Dual-Port Mode” section.
Minor text edits.
Updated graphics.
Updated Table 3–1 and Figure 3–2.
Updated the “Introduction”, “Byte Enable Support”, “Mixed Width Support”,
“Asynchronous Clear”, “Single-Port RAM”, “Simple Dual-Port Mode”, “True Dual-Port
Mode”, “FIFO Mode”, and “Read/Write Clock Mode” sections.
Added introductory sentences to improve search ability.
Removed the Conclusion section.
Minor text edits.
Updated Table 3–2.
Updated Table 3–2.
Removed “Referenced Documents” section.
lists the revision history for this chapter.
“Byte Enable Support”
and
Changes
“Power-Up Conditions and Memory Initialization”
Stratix IV Device Handbook Volume 1
3–23
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