EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 746
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
Bussmann
Quantity:
40 000
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
ALTERA21
Quantity:
53
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- Current page: 746 of 1154
- Download datasheet (32Mb)
2–74
Stratix IV Device Handbook Volume 2: Transceivers
Configuration Example 1: Configuring 24 Channels in Basic (PMA Direct)
×N Mode in the EP4S100G5F45 Device
Each transceiver block has four regular channels and two CMU channels that you can
configure in Basic (PMA Direct) ×N mode. The EP4S100G5F45 device has four
transceiver blocks located on each side of the device allowing configuration of up to
24 channels in Basic (PMA Direct) ×N mode.
When all 24 channels on one side of the device are configured in Basic (PMA Direct)
×N mode, all eight CMU channels (two in each transceiver block) are configured as
PMA-Only channels.
Use the refclk pins in each of the four transceiver blocks as receiver serial data input
pins and configure the CMU PLLs as receiver CDRs when the CMU channel is
configured as a PMA-Only channel. Due to the non-availability of CMU PLLs, you
must use the 6G ATX PLL to generate the high-speed serial and low-speed parallel
transceiver clocks for all 24 channels. Due to the non-availability of a refclk pin, you
must use the left and right, or left or right PLL in VCO bypass mode to provide the
reference clock through the PLL cascade clock line.
For more information about left and right PLL VCO bypass mode, refer to
“Configuration Example 4: Configuring Left and Right, Left, or Right PLL in VCO
Bypass Mode” on page
Figure 2–38
configured in Basic (PMA Direct) ×N mode running at 6.5 Gbps with a 20-bit FPGA
fabric-PMA interface width. Because all 24 channels on the right side of the device are
configured in Basic (PMA Direct) ×N mode, the right PLL_R1 configured in
VCO bypass mode is used to provide the input reference clock to the 6G ATX PLL.
The 6G ATX PLL generates the high-speed serial and low-speed parallel transceiver
clocks that are distributed to the 24 channels though the ×N_Top and ×N_Bottom clock
network. Because the data rate of 6.5 Gbps requires a left and right, or left or right PLL
to meet FPGA fabric-Transmitter PMA interface timing, tx_clkout from one of the 24
channels is phase shifted by 315° using PLL_R2. The phase shifted output clock from
PLL_R2 is used to clock the FPGA fabric logic that generates the transmitter parallel
data and control signals.
shows 24 channels on the right side of the EP4S100G5F45 device
2–79.
Chapter 2: Transceiver Clocking in Stratix IV Devices
February 2011 Altera Corporation
Configuration Examples
Related parts for EP4SGX360FH29C3N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: