EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 203
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
Bussmann
Quantity:
40 000
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
ALTERA21
Quantity:
53
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- Current page: 203 of 1154
- Download datasheet (32Mb)
Chapter 6: I/O Features in Stratix IV Devices
On-Chip Termination Support and I/O Termination Schemes
February 2011 Altera Corporation
LVDS Input OCT (R
Summary of OCT Assignments
f
Stratix IV devices support OCT for differential LVDS input buffers with a nominal
resistance value of 100 Ω , as shown in
in row I/O banks when both the V
do not support OCT R
PLL_L[1,4]_CLK[p,n], and PLL_R[1,4]_CLK[p,n] on the row I/O banks of Stratix IV
devices do not support R
Figure 6–22. Differential Input OCT
For more information about differential on-chip termination, refer to the
Differential I/O Interfaces and DPA in Stratix IV Devices
Table 6–9
Table 6–9. Summary of OCT Assignments in the Quartus II Software
Input Termination
Output Termination
Note to
(1) You can enable differential OCT R
Assignment Name
Table
lists the OCT assignments for the Quartus II software version 9.1 and later.
D
6–9:
)
Transmitter
D.
Parallel 50 Ω with calibration
Differential
Series 25 Ω without calibration
Series 50 Ω without calibration
Series 25 Ω with calibration
Series 40 Ω with calibration
Series 50 Ω with calibration
Series 60 Ω with calibration
Dedicated clock input pairs CLK[1,3,8,10][p,n],
D
termination.
D
in row I/O banks when both V
Value
CCIO
Figure
Z
Z
O
O
and V
= 50 Ω
= 50 Ω
6–22. Differential OCT R
CCPD
is set to 2.5 V. Column I/O banks
CCIO
Input buffers for single-ended and
differential HSTL/SSTL standards
Input buffers for LVDS receivers on
row I/O banks
Output buffers for single-ended
LVTTL/LVCMOS and HSTL/SSTL
standards as well as differential
HSTL/SSTL standards
chapter.
and V
CCPD
100 Ω
Stratix IV Device Handbook Volume 1
are set to 2.5 V.
Applies To
Receiver
(1)
D
can be enabled
High Speed
6–31
Related parts for EP4SGX360FH29C3N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: