EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 1146
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
Bussmann
Quantity:
40 000
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
ALTERA21
Quantity:
53
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Table 1–53. Glossary Table (Part 2 of 4)
Stratix IV Device Handbook Volume 4: Device Datasheet and Addendum
M, N, O
Letter
K, L,
P
Q
R
J
J
JTAG Timing
Specifications
PLL
Specifications
R
L
Subject
—
—
High-speed I/O block: Deserialization factor (width of parallel data bus).
JTAG Timing Specifications:
Diagram of PLL Specifications
Note:
(1) Core Clock can only be fed by dedicated clock input pins or PLL outputs.
Receiver differential input discrete resistor (external to Stratix IV device).
TMS
TDO
TCK
TDI
Core Clock
Key
CLK
Reconfigurable in User Mode
t
JCH
t
JPZX
t
JCP
t
JCL
Switchover
f
IN
External Feedback
N
t
JPCO
f
INPFD
(1)
t
JPSU
Chapter 1: DC and Switching Characteristics for Stratix IV Devices
PFD
M
Definitions
CP
—
—
t
LF
JPH
VCO
f
VCO
t
JPXZ
Counters
C0..C9
CLKOUT Pins
f
f
OUT_EXT
OUT
April 2011 Altera Corporation
GCLK
RCLK
Glossary
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