EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 606
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
Bussmann
Quantity:
40 000
Company:
Part Number:
EP4SGX360FH29C3N
Manufacturer:
ALTERA21
Quantity:
53
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- Current page: 606 of 1154
- Download datasheet (32Mb)
1–162
Figure 1–128. Deskew FIFO in XAUI Mode
Note to
(1) This figure is from IEEE P802.3ae.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
1–128:
After alignment of the first ||A|| column, if three additional aligned ||A||
columns are observed at the output of the deskew FIFOs of the four channels, the
rx_channelaligned signal is asserted high, indicating channel alignment is acquired.
After acquiring channel alignment, if four misaligned ||A|| columns are seen at the
output of the deskew FIFOs in all four channels with no aligned ||A|| columns in
between, the rx_channelaligned signal is de-asserted low, indicating loss-of-channel
alignment.
The deskew FIFO operation in XAUI functional mode is compliant with the PCS
deskew state machine diagram specified in clause 48 of the IEEE P802.3ae, as shown
in
Figure
1–128.
(Note 1)
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
SUDI(![/||A||/])
enable_deskew
enable_deskew
AUDI
AUDI
AUDI
AUDI
AUDI
AUDI
AUDI
AUDI
LOSS_OF_ALIGNMENT
enable_deskew
A
B
C
ALIGN_ACQUIRED_1
ALIGN_ACQUIRED_2
ALIGN_ACQUIRED_3
ALIGN_ACQUIRED_4
align_status
ALIGN_DETECT_1
ALIGN_DETECT_2
ALIGN_DETECT_3
SUDI(![/||A||/])
SUDI(![/||A||/])
SUDI(![/||A||/])
SUDI(![/||A||/])
sync_status OK * SUDI(![/||A||/])
⇐
⇐
⇐
⇐
FAIL
FALSE
FALSE
A
B
C
TRUE
Chapter 1: Transceiver Architecture in Stratix IV Devices
SUDI(![/||A||/])
SUDI(![/||A||/])
SUDI(![/||A||/])
reset +
(sync_status=FAIL * SUDI)
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
February 2011 Altera Corporation
Transceiver Block Architecture
Related parts for EP4SGX360FH29C3N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: