EP4SGX360FH29C3N Altera, EP4SGX360FH29C3N Datasheet - Page 316
EP4SGX360FH29C3N
Manufacturer Part Number
EP4SGX360FH29C3N
Description
IC STRATIX IV FPGA 360K 780HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
Specifications of EP4SGX360FH29C3N
Number Of Logic Elements/cells
353600
Number Of Labs/clbs
14144
Total Ram Bits
22564
Number Of I /o
289
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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8–38
Differential Pin Placement Guidelines
Stratix IV Device Handbook Volume 1
Guidelines for DPA-Enabled Differential Channels
1
To ensure proper high-speed operation, differential pin placement guidelines have
been established. The Quartus II compiler automatically checks that these guidelines
are followed and issues an error message if they are not met.
This section is divided into pin placement guidelines with and without DPA usage
because DPA usage adds some constraints on the placement of high-speed differential
channels.
DPA-enabled differential channels refer to DPA mode or soft-CDR mode; DPA
disabled channels refer to non-DPA mode.
The Stratix IV device family has differential receivers and transmitters in I/O banks
on the left and right sides of the device. Each receiver has a dedicated DPA circuit to
align the phase of the clock to the data phase of its associated channel. When you use
DPA-enabled channels in differential banks, you must adhere to the guidelines listed
in the following sections.
DPA-Enabled Channels and Single-Ended I/Os
When you enable a DPA channel in a bank, both single-ended I/Os and differential
I/O standards are allowed in the bank.
■
■
■
DPA-Enabled Channel Driving Distance
If the number of DPA channels driven by each left and right PLL exceeds 25 LAB
rows, Altera recommends implementing data realignment (bit slip) circuitry for all
the DPA channels.
Using Corner and Center Left and Right PLLs
If a differential bank is being driven by two left and right PLLs, where the corner left
and right PLL is driving one group and the center left and right PLL is driving
another group, there must be at least one row of separation between the two groups
of DPA-enabled channels (refer to
independent frequencies.
Single-ended I/Os are allowed in the same I/O bank, as long as the single-ended
I/O standard uses the same V
Single-ended inputs can be in the same logic array block (LAB) row as a
differential channel using the SERDES circuitry.
DDIO can be placed within the same LAB row as a SERDES differential channel
but half rate DDIO (single data rate) output pins cannot be placed within the same
LAB row as a receiver SERDES differential channel. The input register must be
implemented within the FPGA fabric logic.
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
CCIO
Figure
as the DPA-enabled differential I/O bank.
8–31). The two groups can operate at
Differential Pin Placement Guidelines
February 2011 Altera Corporation
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