EP4CGX110CF23I7 Altera, EP4CGX110CF23I7 Datasheet - Page 31
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EP4CGX110CF23I7
Manufacturer Part Number
EP4CGX110CF23I7
Description
IC CYCLONE IV FPGA 110K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX110CF23I7
Number Of Logic Elements/cells
109424
Number Of Labs/clbs
6839
Total Ram Bits
5490000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Available stocks
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Manufacturer
Quantity
Price
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Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices
LE Operating Modes
LE Operating Modes
Normal Mode
© November 2009 Altera Corporation
In addition to the three general routing outputs, LEs in an LAB have register chain
outputs, which allows registers in the same LAB to cascade together. The register
chain output allows the LUTs to be used for combinational functions and the registers
to be used for an unrelated shift register implementation. These resources speed up
connections between LABs while saving local interconnect resources.
Cyclone IV LEs operate in the following modes:
■
■
The Quartus
functions, such as counters, adders, subtractors, and arithmetic functions, in
conjunction with parameterized functions such as the library of parameterized
modules (LPM) functions. You can also create special-purpose functions that specify
which LE operating mode to use for optimal performance, if required.
Normal mode is suitable for general logic applications and combinational functions.
In normal mode, four data inputs from the LAB local interconnect are inputs to a
four-input LUT
carry-in (cin) or the data3 signal as one of the inputs to the LUT. LEs in normal
mode support packed registers and register feedback.
Figure 2–2
Figure 2–2. Cyclone IV Device LEs in Normal Mode
Normal mode
Arithmetic mode
data1
data2
data3
cin (from cout
of previous LE)
data4
shows LEs in normal mode.
®
II software automatically chooses the appropriate mode for common
(Figure
Packed Register Input
2–2). The Quartus II Compiler automatically selects the
Four-Input
LUT
Register Chain
Connection
Register Bypass
clock (LAB Wide)
sload
ena (LAB Wide)
aclr (LAB Wide)
(LAB Wide)
sclear
Register Feedback
(LAB Wide)
ENA
D
CLRN
Q
Cyclone IV Device Handbook, Volume 1
Row, Column, and
Direct Link Routing
Local Routing
Row, Column, and
Direct Link Routing
Register
Chain Output
2–3
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