EP4CGX110CF23I7 Altera, EP4CGX110CF23I7 Datasheet - Page 142
EP4CGX110CF23I7
Manufacturer Part Number
EP4CGX110CF23I7
Description
IC CYCLONE IV FPGA 110K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX110CF23I7
Number Of Logic Elements/cells
109424
Number Of Labs/clbs
6839
Total Ram Bits
5490000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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6–34
Differential SSTL I/O Standard Support in Cyclone IV Devices
Cyclone IV Device Handbook, Volume 1
f
1
Figure 6–18. LVPECL AC-Coupled Termination
Note to
(1) The LVPECL AC-coupled termination is applicable only when an Altera FPGA transmitter is used.
Figure 6–19
Figure 6–19. LVPECL DC-Coupled Termination
Note to
(1) The LVPECL DC-coupled termination is applicable only when an Altera FPGA transmitter is used.
The differential SSTL I/O standard is a memory-bus standard used for applications
such as high-speed DDR SDRAM interfaces. Cyclone IV devices support differential
SSTL-2 and SSTL-18 I/O standards. The differential SSTL I/O standard requires two
differential inputs with an external reference voltage (VREF) as well as an external
termination voltage (VTT) of 0.5 × V
The differential SSTL output standard is only supported at PLL#_CLKOUT pins using
two single-ended SSTL output buffers (PLL#_CLKOUTp and PLL#_CLKOUTn), with
the second output programmed to have opposite polarity. The differential SSTL input
standard is supported on the GCLK pins only, treating differential inputs as two
single-ended SSTL and only decoding one of them.
For differential SSTL electrical specifications, refer to
Termination” on page 6–15
Figure 6–8 on page 6–15
Figure
Figure
LVPECL Transmitter
6–18:
6–19:
shows the LVPECL DC-coupled termination.
Transmitter
LVPECL
shows the differential SSTL Class I and Class II interface.
and the
0.1 µF
0.1 µF
Cyclone IV Device Datasheet
CCIO
50 Ω
50 Ω
Z 0 = 50 Ω
to which termination resistors are connected.
Z 0 = 50 Ω
(Note 1)
(Note 1)
V ICM
Chapter 6: I/O Features in Cyclone IV Devices
100
“Differential I/O Standard
50
50
Ω
Ω
Ω
© December 2010 Altera Corporation
Cyclone IV Device
LVPECL Receiver
High-Speed I/O Standards Support
Cyclone IV Device
LVPECL Receiver
chapter.
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