EP4CGX110CF23I7 Altera, EP4CGX110CF23I7 Datasheet - Page 133
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4CGX110CF23I7
Manufacturer Part Number
EP4CGX110CF23I7
Description
IC CYCLONE IV FPGA 110K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX110CF23I7
Number Of Logic Elements/cells
109424
Number Of Labs/clbs
6839
Total Ram Bits
5490000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Interface
Table 6–7. Differential I/O Standards Supported in Cyclone IV GX I/O Banks
© December 2010 Altera Corporation
LVDS
RSDS
mini-LVDS
PPDS
BLVDS
LVPECL
Differential SSTL-2
Differential SSTL-18
Differential HSTL-18
Differential HSTL-15
Differential HSTL-12
Notes to
(1) Transmitter and Receiver f
(2) The LVPECL I/O standard is only supported on dedicated clock input pins.
(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock
Differential I/O Standards
pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.
(1)
Table
(2)
6–7:
(3)
(3)
(3)
(3)
(3)
You can use I/O pins and internal logic to implement a high-speed differential
interface in Cyclone IV devices. Cyclone IV devices do not contain dedicated
serialization or deserialization circuitry. Therefore, shift registers, internal
phase-locked loops (PLLs), and I/O cells are used to perform serial-to-parallel
conversions on incoming data and parallel-to-serial conversion on outgoing data. The
differential interface data serializers and deserializers (SERDES) are automatically
constructed in the core logic elements (LEs) with the Quartus II software ALTLVDS
megafunction.
MAX
depend on system topology and performance requirement.
I/O Bank Location
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
4,5,6,7,8
3,4,7,8
5,6
5,6
5,6
5,6
External Resistor
Three Resistors
Three Resistors
Three Resistors
Three Resistors
Single Resistor
Single Resistor
Not Required
Not Required
Not Required
Not Required
Transmitter
Network at
—
—
—
—
—
—
Transmitter (TX)
Cyclone IV Device Handbook, Volume 1
v
v
v
v
v
—
v
v
v
v
v
Receiver (RX)
v
v
v
v
v
v
v
v
—
—
—
6–25
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