EP4CGX110CF23I7 Altera, EP4CGX110CF23I7 Datasheet - Page 129

• Manufacturer Part Number: EP4CGX110CF23I7
• Description: IC CYCLONE IV FPGA 110K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX110CF23I7

• Number Of Logic Elements/cells: 109424
• Number Of Labs/clbs: 6839
• Total Ram Bits: 5490000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -

Chapter 6: I/O Features in Cyclone IV Devices
I/O Banks
Table 6–5. Number of VREF Pins Per I/O Bank for Cyclone IV GX Devices
© December 2010 Altera Corporation
I/O Bank
Notes to
(1) User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as output only.
(2) Bank 9 does not have VREF pin. If input pins with VREF I/O standards are used in bank 9 during user mode, it shares the VREF pin in bank 8.
Device
8(2)
(1)
3
4
5
6
7
Table
148-
QFN
4CGX15
6–5:
1
1
1
1
1
1
1
1
FBGA
169-
Each Cyclone IV I/O bank has its own VCCIO pins. Each I/O bank can support only
one V
single-ended or differential standards can be simultaneously supported in a single
I/O bank, as long as they use the same V
When designing LVTTL/LVCMOS inputs with Cyclone IV devices, refer to the
following guidelines:
■
■
■
Voltage-referenced standards are supported in an I/O bank using any number of
single-ended or differential standards, as long as they use the same V
values. For example, if you choose to implement both SSTL-2 and SSTL-18 in your
Cyclone IV devices, I/O pins using these standards—because they require different
V
can support SSTL-2 and 2.5-V LVCMOS with the V
1.25 V.
When using Cyclone IV devices as a receiver in 3.3-, 3.0-, or 2.5-V LVTTL/LVCMOS
systems, you are responsible for managing overshoot or undershoot to stay in the
absolute maximum ratings and the recommended operating conditions, provided in
the
The PCI clamping diode is enabled by default in the Quartus II software for input
signals with bank V
FBGA
169-
REF
4CGX22
All pins accept input voltage (V
recommended operating conditions provided in the
chapter.
Whenever the input level is higher than the bank V
current.
The LVTTL/LVCMOS I/O standard input pins can only meet the V
levels according to bank voltage level.
Cyclone IV Device Datasheet
values—must be in different banks from each other. However, the same I/O bank
CCIO
1
1
1
1
1
1
FBGA
324-
setting from among 1.2, 1.5, 1.8, 3.0, or 3.3 V. Any number of supported
FBGA
169-
4CGX30
1
1
1
1
1
1
FBGA
324-
CCIO
at 2.5, 3.0, or 3.3 V.
FBGA
484-
4CGX50
3
3
3
3
3
3
chapter.
FBGA
672-
I
) up to a maximum limit (3.6 V), as stated in the
FBGA
484-
4CGX75
CCIO
3
3
3
3
3
3
FBGA
672-
levels for input and output pins.
FBGA
484-
CCIO
CCIO
4CGX110
set to 2.5 V and the V
Cyclone IV Device Datasheet
FBGA
672-
Cyclone IV Device Handbook, Volume 1
3
3
3
3
3
3
, expect higher leakage
FBGA
896-
FBGA
484-
REF
IH
and V
4CGX150
and V
FBGA
672-
REF
3
3
3
3
3
3
CCIO
set to
IL
FBGA
896-
6–21