EP4CGX110CF23I7 Altera, EP4CGX110CF23I7 Datasheet - Page 149
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EP4CGX110CF23I7
Manufacturer Part Number
EP4CGX110CF23I7
Description
IC CYCLONE IV FPGA 110K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX110CF23I7
Number Of Logic Elements/cells
109424
Number Of Labs/clbs
6839
Total Ram Bits
5490000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
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Figure 7–1. Cyclone IV Devices External Memory Data Path
Note to
(1) All clocks shown here are global clocks.
© December 2010 Altera Corporation
CYIV-51007-2.2
Figure
7–1:
f
PLL
1
-90° Shifted Clock
OE
This chapter describes the memory interface pin support and the external memory
interface features of Cyclone
In addition to an abundant supply of on-chip memory, Cyclone IV devices can easily
interface with a broad range of external memory devices, including DDR2 SDRAM,
DDR SDRAM, and QDR II SRAM. External memory devices are an important system
component of a wide range of image processing, storage, communications, and
general embedded applications.
Altera recommends that you construct all DDR2 or DDR SDRAM external memory
interfaces using the Altera
controller function using the Altera DDR2 or DDR SDRAM memory controllers,
third-party controllers, or a custom controller for unique application needs.
Cyclone IV devices support QDR II interfaces electrically, but Altera does not supply
controller or physical layer (PHY) megafunctions for QDR II interfaces.
This chapter includes the following sections:
■
■
For more information about supported maximum clock rate, device and pin planning,
IP implementation, and device termination, refer to the
Handbook.
Figure 7–1
in Cyclone IV devices.
Register
System Clock
IOE
Register
“Cyclone IV Devices Memory Interfaces Pin Support” on page 7–2
“Cyclone IV Devices Memory Interfaces Features” on page 7–12
IOE
GND
V CC
Capture Clock
shows the block diagram of a typical external memory interface data path
Register
Register
IOE
IOE
DQS/CQ/CQn
®
OE
ALTMEMPHY megafunction. You can implement the
®
IV devices.
7. External Memory Interfaces in
Register
(Note 1)
IOE
Register
IOE
DataA
DataB
Register
Register
IOE
IOE
DQ
Cyclone IV Devices
External Memory Interface
Cyclone IV Device Handbook, Volume 1
Register
Register
LE
LE
Register
LE
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