EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 82
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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Digital Signal Processing Block
2–68
Stratix Device Handbook, Volume 1
single DSP block can implement two sums or differences from two
18 × 18-bit multipliers each or four sums or differences from two 9 × 9-bit
multipliers each.
You can use the two-multipliers adder mode for complex multiplications,
which are written as:
The two-multipliers adder mode allows a single DSP block to calculate
the real part [(a × c) – (b × d)] using one subtractor and the imaginary part
[(a × d) + (b × c)] using one adder, for data widths up to 18 bits. Two
complex multiplications are possible for data widths up to 9 bits using
four adder/subtractor/accumulator blocks.
two-multipliers adder.
Figure 2–38. Two-Multipliers Adder Mode Implementing Complex Multiply
Four-Multipliers Adder Mode
In the four-multipliers adder mode, the DSP block adds the results of two
first -stage adder/subtractor blocks. One sum of four 18 × 18-bit
multipliers or two different sums of two sets of four 9 × 9-bit multipliers
can be implemented in a single DSP block. The product width for each
multiplier must be the same size. The four-multipliers adder mode is
useful for FIR filter applications.
adder mode.
(a + jb) × (c + jd) = [(a × c) – (b × d)] + j × [(a × d) + (b × c)]
18
18
18
18
A
C
B
D
A
D
B
C
18
18
18
18
18
18
18
18
36
36
36
36
Figure 2–39
Subtractor
Adder
DSP Block
Figure 2–38
shows the four multipliers
37
37
(Imaginary Part)
(A × C) − (B × D)
(A × D) + (B × C)
(Real Part)
Altera Corporation
shows an 18-bit
July 2005
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