EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 159
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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SignalTap II
Embedded Logic
Analyzer
Configuration
Altera Corporation
July 2005
f
1
For more information on JTAG, see the following documents:
■
■
Stratix devices feature the SignalTap II embedded logic analyzer, which
monitors design operation over a period of time through the IEEE Std.
1149.1 (JTAG) circuitry. You can analyze internal logic at speed without
bringing internal signals to the I/O pins. This feature is particularly
important for advanced packages, such as FineLine BGA
because it can be difficult to add a connection to a pin during the
debugging process after a board is designed and manufactured.
The logic, circuitry, and interconnects in the Stratix architecture are
configured with CMOS SRAM elements. Altera
reconfigurable. Because every device is tested with a high-coverage
production test program, you do not have to perform fault testing and can
focus on simulation and design verification.
Stratix devices are configured at system power-up with data stored in an
Altera serial configuration device or provided by a system controller.
Altera offers in-system programmability (ISP)-capable configuration
devices that configure Stratix devices via a serial data stream. Stratix
devices can be configured in under 100 ms using 8-bit parallel data at
100 MHz. The Stratix device’s optimized interface allows
microprocessors to configure it serially or in parallel, and synchronously
or asynchronously. The interface also enables microprocessors to treat
Stratix devices as memory and configure them by writing to a virtual
memory location, making reconfiguration easy. After a Stratix device has
been configured, it can be reconfigured in-circuit by resetting the device
and loading new data. Real-time changes can be made during system
operation, enabling innovative reconfigurable computing applications.
Operating Modes
The Stratix architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices
Jam Programming & Test Language Specification
Stratix, Stratix II, Cyclone
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix, Stratix II,
Cyclone, and Cyclone II devices are in the 18th or after they will
fail configuration. This does not affect SignalTap II.
®
, and Cyclone II devices must be
Stratix Device Handbook, Volume 1
®
devices are
Configuration & Testing
®
packages,
3–5
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