EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 101
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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Figure 2–52. Stratix Enhanced PLL
Notes to
(1)
(2)
(3)
(4)
Altera Corporation
July 2005
INCLK0
INCLK1
External feedback is available in PLLs 5 and 6.
This single-ended external output is available from the g0 counter for PLLs 11 and 12.
These four counters and external outputs are available in PLLs 5 and 6.
This connection is only available on EP1S40 and larger Stratix devices. For example, PLLs 5 and 11 are adjacent and
PLLs 6 and 12 are adjacent. The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11
and 12.
Figure
Switch-Over
Circuitry
Clock
2–52:
FBIN
/n
(1)
Δt
Enhanced PLLs
Stratix devices contain up to four enhanced PLLs with advanced clock
management features.
Phase Frequency
Detector
PFD
Charge
Pump
VCO Phase Selection
Selectable at Each
PLL Output Port
Lock Detect
& Filter
VCO Phase Selection
Affecting All Outputs
Spectrum
Δt
Spread
Loop
Filter
/m
Figure 2–52
From Adjacent PLL
VCO
8
shows a diagram of the enhanced PLL.
Post-Scale
Counters
/g0
/g1
/g2
/g3
/e0
/e2
/e3
/e1
Stratix Device Handbook, Volume 1
/l0
/l1
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Δt
Programmable
Time Delay on
Each PLL Port
4
4
Stratix Architecture
I/O buffers (2)
To I/O buffers or general
routing
Regional
Clocks
Global
Clocks
I/O Buffers (3)
2–87
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