EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 130
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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I/O Structure
2–116
Stratix Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
DDR SDRAM (1),
DDR SDRAM - side
banks (2), (3),
RLDRAM II
QDR SRAM
QDRII SRAM
ZBT SRAM
Table 2–25. External RAM Support in EP1S10 through EP1S40 Devices
DDR Memory Type
These maximum clock rates apply if the Stratix device uses DQS phase-shift circuitry to interface with DDR
SDRAM. DQS phase-shift circuitry is only available in the top and bottom I/O banks (I/O banks 3, 4, 7, and 8).
For more information on DDR SDRAM, see AN 342: Interfacing DDR SDRAM with Stratix & Stratix GX Devices.
DDR SDRAM is supported on the Stratix device side I/O banks (I/O banks 1, 2, 5, and 6) without dedicated DQS
phase-shift circuitry. The read DQS signal is ignored in this mode.
These performance specifications are preliminary.
This device does not support RLDRAM II.
For more information on QDR or QDRII SRAM, see AN 349: QDR SRAM Controller Reference Design for Stratix &
Stratix GX Devices.
For more information on ZBT SRAM, see AN 329: ZBT SRAM Controller Reference Design for Stratix & Stratix GX
Devices.
Table
(4)
(7)
(6)
(6)
(4)
2–25:
(2)
SSTL-2
SSTL-2
1.8-V HSTL
1.5-V HSTL
1.5-V HSTL
LVTTL
Standard
I/O
Tables 2–25
SDRAM, RLDRAM II, QDR SRAM, QDRII SRAM, and ZBT SRAM
interfaces in EP1S10 through EP1S40 devices and in EP1S60 and EP1S80
devices. The DDR SDRAM and QDR SRAM numbers in
been verified with hardware characterization with third-party DDR
SDRAM and QDR SRAM devices over temperature and voltage
extremes.
Flip-Chip Flip-Chip
-5 Speed
Grade
200
150
200
167
200
200
and
2–26
-6 Speed Grade
167
133
167
167
200
(5)
show the performance specification for DDR
Maximum Clock Rate (MHz)
Wire-
Bond
133
110
133
133
200
(5)
-7 Speed Grade
Flip-
Chip
133
133
133
133
167
(5)
Wire-
Bond
100
100
167
100
100
(5)
Altera Corporation
Table 2–25
-8 Speed Grade
Flip-
Chip
100
100
100
100
133
(5)
July 2005
Wire-
Bond
100
100
100
100
133
(5)
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