EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 129
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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Figure 2–68. Output Timing Diagram in DDR Mode
Altera Corporation
July 2005
From Internal
Registers
DDR output
f
CLK
A
B
The Stratix IOE operates in bidirectional DDR mode by combining the
DDR input and DDR output configurations. Stratix device I/O pins
transfer data on a DDR bidirectional bus to support DDR SDRAM. The
negative-edge-clocked OE register holds the OE signal inactive until the
falling edge of the clock. This is done to meet DDR SDRAM timing
requirements.
External RAM Interfacing
Stratix devices support DDR SDRAM at up to 200 MHz (400-Mbps data
rate) through dedicated phase-shift circuitry, QDR and QDRII SRAM
interfaces up to 167 MHz, and ZBT SRAM interfaces up to 200 MHz.
Stratix devices also provide preliminary support for reduced latency
DRAM II (RLDRAM II) at rates up to 200 MHz through the dedicated
phase-shift circuitry.
1
To find out more about the DDR SDRAM specification, see the JEDEC
web site (www.jedec.org). For information on memory controller
megafunctions for Stratix devices, see the Altera web site
(www.altera.com). See AN 342: Interfacing DDR SDRAM with Stratix &
Stratix GX Devices for more information on DDR SDRAM interface in
Stratix. Also see AN 349: QDR SRAM Controller Reference Design for
Stratix & Stratix GX Devices and AN 329: ZBT SRAM Controller Reference
Design for Stratix & Stratix GX Devices.
In addition to the required signals for external memory
interfacing, Stratix devices offer the optional clock enable signal.
By default the Quartus II software sets the clock enable signal
high, which tells the output register to update with new values.
The output registers hold their own values if the design sets the
clock enable signal low. See
A1
B1
B1
A2
B2
A1
B2
A3
B3
A2
B3
A4
B4
Figure
Stratix Device Handbook, Volume 1
A3
2–64.
Stratix Architecture
2–115
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