EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 243
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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Altera Corporation
January 2006
Decrease input delay
to internal cells
Decrease input delay
to input register
Decrease input delay
to output register
Increase delay to
output pin
Increase delay to
output enable pin
Increase output clock
enable delay
Increase input clock
enable delay
Increase output
enable clock enable
delay
Increase t
output pin
Table 4–109. Stratix IOE Programmable Delays on Column Pins
Parameter
ZX
delay to
Off
Small
Medium
Large
On
Off
On
Off
On
Off
On
Off
On
Off
Small
Large
On
Off
Small
Large
On
Off
Small
Large
On
Off
On
Setting
Tables 4–109
IOE programmable delays. These delays are controlled with the
Quartus II software logic options listed in the Parameter column.
-5 Speed Grade -6 Speed Grade -7 Speed Grade -8 Speed Grade
Min
3,970
3,390
2,810
3,900
1,240
1,016
1,016
1,016
1,016
1,016
1,016
2,199
and
Max
224
224
397
338
540
540
540
0
0
0
0
0
0
0
0
4–110
Min
show the adder delays for the column and row
4,367
3,729
3,091
4,290
1,364
1,118
1,118
1,118
1,118
1,118
1,118
2,309
Max
235
235
417
372
594
594
594
0
0
0
0
0
0
0
0
Note (1)
Min
Stratix Device Handbook, Volume 1
DC & Switching Characteristics
5,022
4,288
3,554
4,933
1,568
1,285
1,285
1,285
1,285
1,285
1,285
2,309
Max
270
270
417
427
683
683
683
0
0
0
0
0
0
0
0
Min
5,908
5,045
4,181
5,804
1,845
1,512
1,512
1,512
1,512
1,512
1,512
2,309
Max
318
318
417
503
804
804
804
0
0
0
0
0
0
0
0
Unit
4–73
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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