EP1S10F484C7N Altera, EP1S10F484C7N Datasheet - Page 108
![IC STRATIX FPGA 10K LE 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP1S10F484C7N
Manufacturer Part Number
EP1S10F484C7N
Description
IC STRATIX FPGA 10K LE 484-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S10F484C7N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
335
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
10570
# I/os (max)
335
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
10570
Ram Bits
920448
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
No. Of Macrocells
10570
Family Type
Stratix
No. Of I/o's
335
Clock Management
DLL, PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
420MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S10F484C7N
Manufacturer:
ALTERA
Quantity:
455
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PLLs & Clock Networks
2–94
Stratix Device Handbook, Volume 1
Any of the four external output counters can drive the single-ended or
differential clock outputs for PLLs 5 and 6. This means one counter or
frequency can drive all output pins available from PLL 5 or PLL 6. Each
pair of output pins (four pins total) has dedicated VCC and GND pins to
reduce the output clock’s overall jitter by providing improved isolation
from switching I/O pins.
For PLLs 5 and 6, each pin of a single-ended output pair can either be in
phase or 180° out of phase. The clock output pin pairs support the same
I/O standards as standard output pins (in the top and bottom banks) as
well as LVDS, LVPECL, 3.3-V PCML, HyperTransport technology,
differential HSTL, and differential SSTL.
standards the enhanced PLL clock pins support. When in single-ended or
differential mode, the two outputs operate off the same power supply.
Both outputs use the same standards in single-ended mode to maintain
performance. You can also use the external clock output pins as user
output pins if external enhanced PLL clocking is not needed.
LVTTL
LVCMOS
2.5 V
1.8 V
1.5 V
3.3-V PCI
3.3-V PCI-X 1.0
LVPECL
3.3-V PCML
LVDS
HyperTransport technology
Differential HSTL
Differential SSTL
3.3-V GTL
3.3-V GTL+
1.5-V HSTL Class I
Table 2–20. I/O Standards Supported for Enhanced PLL Pins (Part 1 of 2)
I/O Standard
INCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
FBIN
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Table 2–20
Input
PLLENABLE
shows which I/O
v
v
Altera Corporation
EXTCLK
July 2005
Output
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
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