EP1C20F324C7N Altera, EP1C20F324C7N Datasheet - Page 9

IC CYCLONE FPGA 20K LE 324-FBGA

EP1C20F324C7N

Manufacturer Part Number
EP1C20F324C7N
Description
IC CYCLONE FPGA 20K LE 324-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet

Specifications of EP1C20F324C7N

Number Of Logic Elements/cells
20060
Number Of Labs/clbs
2006
Total Ram Bits
294912
Number Of I /o
233
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1678

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1C20F324C7N
Manufacturer:
ALTERA
Quantity:
784
Part Number:
EP1C20F324C7N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1C20F324C7N
Manufacturer:
ALTERA
0
Part Number:
EP1C20F324C7N
Manufacturer:
ALTERA
Quantity:
20 000
Logic Array
Blocks
Figure 2–2. Cyclone LAB Structure
Altera Corporation
May 2008
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local
interconnect, look-up table (LUT) chain, and register chain connection
lines. The local interconnect transfers signals between LEs in the same
LAB. LUT chain connections transfer the output of one LE's LUT to the
adjacent LE for fast sequential LUT connections within the same LAB.
Register chain connections transfer the output of one LE's register to the
adjacent LE's register within a LAB. The Quartus
associated logic within a LAB or adjacent LABs, allowing the use of local,
LUT chain, and register chain connections for performance and area
efficiency.
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, PLLs, and M4K RAM
blocks from the left and right can also drive a LAB's local interconnect
through the direct link connection. The direct link connection feature
minimizes the use of row and column interconnects, providing higher
Figure 2–2
LAB
details the Cyclone LAB.
Local Interconnect
Row Interconnect
®
II Compiler places
Logic Array Blocks
Column Interconnect
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Preliminary
2–3

Related parts for EP1C20F324C7N