EP1C20F324C7N Altera, EP1C20F324C7N Datasheet - Page 47

IC CYCLONE FPGA 20K LE 324-FBGA

EP1C20F324C7N

Manufacturer Part Number
EP1C20F324C7N
Description
IC CYCLONE FPGA 20K LE 324-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet

Specifications of EP1C20F324C7N

Number Of Logic Elements/cells
20060
Number Of Labs/clbs
2006
Total Ram Bits
294912
Number Of I /o
233
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1678

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Figure 2–28. Row I/O Block Connection to the Interconnect
Notes to
(1)
(2)
Altera Corporation
May 2008
The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output enables,
io_coe[2..0], three input clock enables, io_cce_in[2..0], three output clock enables, io_cce_out[2..0],
three clocks, io_cclk[2..0], three asynchronous clear signals, io_caclr[2..0], and three synchronous clear
signals, io_csclr[2..0].
Each of the three IOEs in the row I/O block can have one io_datain input (combinatorial or registered) and one
comb_io_datain (combinatorial) input.
LAB Local
Interconnect
Figure
R4 Interconnects
to Adjacent LAB
Interconnect
Direct Link
2–28:
LAB
io_datain[2..0] and
comb_io_datain[2..0] (2)
C4 Interconnects
from Adjacent LAB
Interconnect
Direct Link
I/O Block Local
Interconnect
io_clk[5:0]
21
I/O Block
Row I/O Block
Contains up to
Row
Three IOEs
21 Data and
Control Signals
from Logic Array (1)
I/O Structure
Preliminary
2–41

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