EP2C5F256C8 Altera, EP2C5F256C8 Datasheet - Page 19

• Manufacturer Part Number: EP2C5F256C8
• Description: IC CYCLONE II FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C5F256C8

• Number Of Logic Elements/cells: 4608
• Number Of Labs/clbs: 288
• Total Ram Bits: 119808
• Number Of I /o: 158
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 4608
• # I/os (max): 158
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 4608
• Ram Bits: 119808
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• No. Of Macrocells: 4608
• Family Type: Cyclone II
• No. Of I/o's: 158
• Clock Management: PLL
• I/o Supply Voltage: 3.6V
• Operating Frequency Max: 320MHz
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1446

Logic Array
Blocks
Figure 2–5. Cyclone II LAB Structure
Altera Corporation
February 2007
Direct link
interconnect
from adjacent
block
Direct link
interconnect
to adjacent
block
Each LAB consists of the following:
■
■
■
■
■
The local interconnect transfers signals between LEs in the same LAB.
Register chain connections transfer the output of one LE’s register to the
adjacent LE’s register within an LAB. The Quartus II Compiler places
associated logic within an LAB or adjacent LABs, allowing the use of
local, and register chain connections for performance and area efficiency.
Figure 2–5
16 LEs
LAB control signals
LE carry chains
Register chains
Local interconnect
LAB
shows the Cyclone II LAB.
Local Interconnect
Cyclone II Device Handbook, Volume 1
Row Interconnect
Cyclone II Architecture
Direct link
interconnect
from adjacent
block
Direct link
interconnect
to adjacent
block
Column
Interconnect
2–7