EP2C5F256C8 Altera, EP2C5F256C8 Datasheet - Page 4

• Manufacturer Part Number: EP2C5F256C8
• Description: IC CYCLONE II FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C5F256C8

• Number Of Logic Elements/cells: 4608
• Number Of Labs/clbs: 288
• Total Ram Bits: 119808
• Number Of I /o: 158
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 4608
• # I/os (max): 158
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 4608
• Ram Bits: 119808
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• No. Of Macrocells: 4608
• Family Type: Cyclone II
• No. Of I/o's: 158
• Clock Management: PLL
• I/o Supply Voltage: 3.6V
• Operating Frequency Max: 320MHz
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1446

Features
Features
1–2
Cyclone II Device Handbook, Volume 1
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Cyclone II devices include a powerful FPGA feature set optimized for
low-cost applications including a wide range of density, memory,
embedded multiplier, and packaging options. Cyclone II devices support
a wide range of common external memory interfaces and I/O protocols
required in low-cost applications. Parameterizable IP cores from Altera
and partners make using Cyclone II interfaces and protocols fast and easy.
The Cyclone II device family offers the following features:
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DSP intellectual property (IP) cores
DSP Builder interface to The Mathworks Simulink and Matlab
design environment
DSP Development Kit, Cyclone II Edition
High-density architecture with 4,608 to 68,416 LEs
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Embedded multipliers
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Advanced I/O support
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M4K embedded memory blocks
Up to 1.1 Mbits of RAM available without reducing available
logic
4,096 memory bits per block (4,608 bits per block including 512
parity bits)
Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32,
and ×36
True dual-port (one read and one write, two reads, or two
writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes
Byte enables for data input masking during writes
Up to 260-MHz operation
Up to 150 18- × 18-bit multipliers are each configurable as two
independent 9- × 9-bit multipliers with up to 250-MHz
performance
Optional input and output registers
High-speed differential I/O standard support, including LVDS,
RSDS, mini-LVDS, LVPECL, differential HSTL, and differential
SSTL
Single-ended I/O standard support, including 2.5-V and 1.8-V,
SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI
and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-,
and 1.8-V LVTTL
Peripheral Component Interconnect Special Interest Group (PCI
SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V
operation at 33 or 66 MHz for 32- or 64-bit interfaces
PCI Express with an external TI PHY and an Altera PCI Express
×1 Megacore
®
function
Altera Corporation
February 2008