EP2C5F256C8 Altera, EP2C5F256C8 Datasheet - Page 155

IC CYCLONE II FPGA 5K 256-FBGA

EP2C5F256C8

Manufacturer Part Number
EP2C5F256C8
Description
IC CYCLONE II FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C5F256C8

Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
158
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
4608
# I/os (max)
158
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
4608
Ram Bits
119808
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
256
Package Type
FBGA
No. Of Macrocells
4608
Family Type
Cyclone II
No. Of I/o's
158
Clock Management
PLL
I/o Supply Voltage
3.6V
Operating Frequency Max
320MHz
Rohs Compliant
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1446

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Altera Corporation
February 2008
Notes to
(1)
(2)
t
t
t
t
t
t
t
t
t
t
t
t
t
J C P
J C H
J C L
J P S U
J P H
J P C O
J P Z X
J P X Z
J S S U
J S H
J S C O
J S Z X
J S X Z
Table 5–53. Cyclone II JTAG Timing Parameters and Values
Symbol
This information is preliminary.
This specification is shown for 3.3-V LVTTL/LVCMOS and 2.5-V LVTTL/LVCMOS operation of the JTAG pins. For
1.8-V LVTTL/LVCMOS and 1.5-V LVCMOS, the JTAG port and capture register clock setup time is 3 ns and port
clock to output time is 15 ns.
Table
TCK
TCK
TCK
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
5–53:
f
clock period
clock high time
clock low time
Table 5–53
devices.
1
For more information on JTAG, refer to the
Boundary-Scan Testing for Cyclone II Devices
Handbook.
Parameter
(2)
(2)
Cyclone II devices must be within the first 17 devices in a JTAG
chain. All of these devices have the same JTAG controller. If any
of the Cyclone II devices are in the 18th position or after they will
fail configuration. This does not affect the SignalTap
analyzer.
(2)
shows the JTAG timing parameters and values for Cyclone II
(2)
(2)
DC Characteristics and Timing Specifications
Min
Cyclone II Device Handbook, Volume 1
20
20
10
10
40
5
5
chapter in the Cyclone II
IEEE 1149.1 (JTAG)
Max
13
13
13
25
25
25
®
II logic
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5–65

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