EP2C5F256C8 Altera, EP2C5F256C8 Datasheet - Page 121

• Manufacturer Part Number: EP2C5F256C8
• Description: IC CYCLONE II FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIr

Specifications of EP2C5F256C8

• Number Of Logic Elements/cells: 4608
• Number Of Labs/clbs: 288
• Total Ram Bits: 119808
• Number Of I /o: 158
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone® II
• Number Of Logic Blocks/elements: 4608
• # I/os (max): 158
• Frequency (max): 402.58MHz
• Process Technology: 90nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 4608
• Ram Bits: 119808
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• No. Of Macrocells: 4608
• Family Type: Cyclone II
• No. Of I/o's: 158
• Clock Management: PLL
• I/o Supply Voltage: 3.6V
• Operating Frequency Max: 320MHz
• Rohs Compliant: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1446

Altera Corporation
February 2008
Notes to
(1)
(2)
(3)
(4)
Input Delay
from Pin to
Input
Register
Delay from
Output
Register to
Output Pin
Parameter
Table 5–37. Cyclone II IOE Programmable Delay on Row Pins
The incremental values for the settings are generally linear. For exact values of each setting, use the latest version
of the Quartus II software.
The minimum and maximum offset timing numbers are in reference to setting “0” as available in the Quartus II
software.
The value in the first row represents the fast corner timing parameter for industrial and automotive devices. The
second row represents the fast corner timing parameter for commercial devices.
The value in the first row is for automotive devices. The second row is for commercial devices.
Table 5–37
Pad ->
I/O input
register
I/O
output
register -
> Pad
Affected
Paths
:
Settings
Number
of
8
2
Default Capacitive Loading of Different I/O Standards
Refer to
standards.
LVTTL
LVCMOS
2.5V
1.8V
1.5V
PCI
PCI-X
SSTL_2_CLASS_I
SSTL_2_CLASS_II
SSTL_18_CLASS_I
Table 5–38. Default Loading of Different I/O Standards for Cyclone II Device
(Part 1 of 2)
Fast Corner
Offset
Min
0
0
0
0
Table 5–38
Offset
2669
2802
Max
308
324
I/O Standard
(3)
for default capacitive loading of different I/O
Offset
Min
—
—
0
0
–6 Speed
Grade
Offset
DC Characteristics and Timing Specifications
4482
Max
572
—
—
Notes
Cyclone II Device Handbook, Volume 1
Offset
Min
(1),
0
0
0
0
–7 Speed
Grade
(2)
Offset
Capacitive Load
(4)
4834
4671
Max
(Part 2 of 2)
648
626
10
10
0
0
0
0
0
0
0
0
–8 Speed Grade
Offset
Min
—
—
0
0
Offset
4859
Max
682
—
—
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Unit
5–31
ps
ps
ps
ps