EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 82

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

5–18
Clock Switchover
Cyclone III Device Handbook, Volume 1
f
If you use the SignalTap
locked signal goes low only when areset is deasserted. If the areset signal is not
enabled, the extra logic is not implemented in the ALTPLL megafunction.
For more information about the PLL control signals, refer to the
User
The clock switchover feature allows the PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application,
such as a system that turns on the redundant clock if the previous clock stops
running. Your design can automatically perform clock switchover when the clock is
no longer toggling, or based on the user control signal, clkswitch.
Automatic Clock Switchover
Cyclone III device family PLLs support a fully configurable clock switchover
capability.
When the current reference clock is not present, the clock-sense block automatically
switches to the backup clock for PLL reference. The clock switchover circuit also
sends out three status signals—clkbad[0], clkbad[1], and activeclock—from
the PLL to implement a custom switchover circuit. You can select a clock source at the
backup clock by connecting it to the inclk1 port of the PLL in your design.
Figure 5–14
Figure 5–14. Automatic Clock Switchover Circuit
Guide.
inclk1
inclk0
shows the block diagram of the switchover circuit built into the PLL.
muxout
®
II tool to probe the locked signal before the D flip-flop, the
clksw
n Counter
Sense
Clock
Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family
refclk
Switchover
Machine
State
© December 2009 Altera Corporation
PFD
ALTPLL Megafunction
clkswitch
(provides manual
switchover support)
fbclk
clkbad0
clkbad1
Activeclock
Hardware Features