EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 144
EP3C5F256C8N
Manufacturer Part Number
EP3C5F256C8N
Description
IC CYCLONE III FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
Specifications of EP3C5F256C8N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
321
Family Type
Cyclone III
No. Of I/o's
182
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2423
EP3C5F256C8N
EP3C5F256C8N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA
Quantity:
853
Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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7–20
Table 7–6. Chapter Revision History (Part 2 of 2)
Cyclone III Device Handbook, Volume 1
May 2008
July 2007
March 2007
Date
Version
1.2
1.1
1.0
Changes include addition of BLVD information
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Initial release.
Updated “Introduction” section with BLVDS information.
Updated Figure 7–1 with BLVDS information and added Note 5.
Updated Table 7–1 and added BLVDS information.
Updated “Cyclone III High-Speed I/O Banks” section with BLVDS information.
Updated Table 7–2 and 7–6.
Added new section “BLVDS I/O Standard Support in Cyclone III Devices”.
Updated Note 4 to Figure 7–4.
Updated Note 1 to Figure 7–10.
Updated Note 1 to Figure 7–11.
Updated Note 1 to Figure 7–14.
Updated “Mini-LVDS I/O Standard Support in Cyclone III Devices” section.
Updated Note 1 to Figure 7–17.
Updated “LVPECL I/O Support in Cyclone III Devices” section.
Added new Figure 7–18.
Added note that PLL output clock pins do not support Class II type of
selected differential I/O standards.
Added Table 8–3 that lists the number of differential channels which are
migratable across densities and packages.
Updated (Note 4) to Figure 7–1.
Updated (Note 3) to Table 7–1.
Added new Table 7–3.
Added (Note 1) to Figure 7–21.
Added (Note 1) to Figure 7–23.
Added chapter TOC and “Referenced Documents” section.
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Changes Made
© December 2009 Altera Corporation
Chapter Revision History
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