EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 127
![IC CYCLONE III FPGA 5K 256-FBGA](/photos/6/70/67063/544-256-fbga_sml.jpg)
EP3C5F256C8N
Manufacturer Part Number
EP3C5F256C8N
Description
IC CYCLONE III FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIIr
Datasheets
1.EP3C5F256C8N.pdf
(5 pages)
2.EP3C5F256C8N.pdf
(34 pages)
3.EP3C5F256C8N.pdf
(66 pages)
4.EP3C5F256C8N.pdf
(14 pages)
5.EP3C5F256C8N.pdf
(76 pages)
6.EP3C10M164C8N.pdf
(350 pages)
Specifications of EP3C5F256C8N
Number Of Logic Elements/cells
5136
Number Of Labs/clbs
321
Total Ram Bits
423936
Number Of I /o
182
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
321
Family Type
Cyclone III
No. Of I/o's
182
I/o Supply Voltage
3.3V
Operating Frequency Max
402MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
For Use With
544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2423
EP3C5F256C8N
EP3C5F256C8N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA
Quantity:
853
Part Number:
EP3C5F256C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
- EP3C5F256C8N PDF datasheet
- EP3C5F256C8N PDF datasheet #2
- EP3C5F256C8N PDF datasheet #3
- EP3C5F256C8N PDF datasheet #4
- EP3C5F256C8N PDF datasheet #5
- EP3C10M164C8N PDF datasheet #6
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Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Interface
Table 7–1. Differential I/O Standards Supported in Cyclone III Device Family I/O Banks
© December 2009
LVDS
RSDS
mini-LVDS
PPDS
BLVDS
LVPECL
Differential SSTL-2
Differential SSTL-18
Differential HSTL-18
Differential HSTL-15
Differential HSTL-12
Notes to
(1) Transmitter and Receiver F
(2) The LVPECL I/O standard is only supported on dedicated clock input pins.
(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock
Differential I/O Standards
pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.
(1)
Table
(2)
7–1:
Altera Corporation
(3)
(3)
(3)
(3)
(3)
Table 7–1
family.
You can use I/O pins and internal logic to implement a high-speed differential
interface in the Cyclone III device family. The Cyclone III device family does not
contain dedicated serialization or deserialization circuitry. Therefore, shift registers,
internal phase-locked loops (PLLs), and I/O cells are used to perform
serial-to-parallel conversions on incoming data and parallel-to-serial conversion on
outgoing data. The differential interface data serializers and deserializers (SERDES)
are automatically constructed in the core logic elements (LEs) with the Quartus
software ALTLVDS megafunction.
MAX
depend on system topology and performance requirement.
lists which I/O bank supports these I/O standards in the Cyclone III device
I/O Bank Location
3, 4, 7, 8
1,2,5,6
1,2,5,6
1,2,5,6
1,2,5,6
All
All
All
All
All
All
All
All
All
All
All
External Resistor
Three Resistors
Three Resistors
Three Resistors
Three Resistors
Single Resistor
Single Resistor
Not Required
Not Required
Not Required
Not Required
Transmitter
Network at
NA
NA
NA
NA
NA
NA
Transmitter (TX)
Cyclone III Device Handbook, Volume 1
Supported
Yes
Yes
Yes
Yes
Yes
Not
Yes
Yes
Yes
Yes
Yes
Receiver (RX)
Supported
Supported
Supported
Yes
Not
Not
Not
Yes
Yes
Yes
Yes
Yes
Yes
Yes
®
II
7–3
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