EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 158

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

8–14
Chapter Revision History
Table 8–3. Chapter Revision History
Cyclone III Device Handbook, Volume 1
January 2010
December 2009
July 2009
June 2009
October 2008
May 2008
July 2007
March 2007
Date
f
For more information about Cyclone III device family PLL, refer to the
and PLLs in Cyclone III Devices
Table 8–3
Version
2.3
2.2
2.1
2.0
1.3
1.2
1.1
1.0
lists the revision history for this chapter.
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Minor changes to the text.
Made minor correction to the part number.
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Initial release.
Removed Tables 8-1, 8-2, 8-3, and 8-4.
Changed links to reference
Updated chapter part number.
Updated “Introduction” on page 8–1.
Updated Table 8–1 on page 8–1, Table 8–2 on page 8–2, Table 8–3 on
page 8–3, Table 8–4 on page 8–4, and Table 8–5 on page 8–7. Updated notes
to Table 8–6 on page 8–10. Updated “Data and Data Clock/Strobe Pins” on
page 8–5.
Updated note to Figure 8–2 on page 8–12.
Updated “Optional Parity, DM, and Error Correction Coding Pins” on
page 8–13.
Updated “Address and Control/Command Pins” on page 8–14.
Updated “Introduction”, “DDR Input Registers” and “Conclusion” sections.
Updated chapter to new template.
Added (Note 4) to Figure 8–3.
Updated Table 8–3 and Table 8-5. Added new Table 8–4.
Updated (Note 1) to Figure 8-4. Updated Figure 8–5 and 8–14.
Updated “Data and Data Clock/Strobe Pins” section.
Updated Table 8–5.
Added chapter TOC and “Referenced Documents” section.
chapter.
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Literature: External Memory Interfaces
Changes Made
© January 2010 Altera Corporation
Chapter Revision History
Clock Networks
.