EP3C5F256C8N Altera, EP3C5F256C8N Datasheet - Page 42

• Manufacturer Part Number: EP3C5F256C8N
• Description: IC CYCLONE III FPGA 5K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C5F256C8N

• Number Of Logic Elements/cells: 5136
• Number Of Labs/clbs: 321
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• No. Of Logic Blocks: 321
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2423; EP3C5F256C8N

3–6
Cyclone III Device Handbook, Volume 1
Figure 3–3
feeds back to its input using a multiplexer. The multiplexer output is selected by the
address clock enable (addressstall) signal.
Figure 3–3. Cyclone III Device Family Address Clock Enable Block Diagram
The address clock enable is typically used to improve the effectiveness of cache
memory applications during a cache-miss. The default value for the address clock
enable signals is low.
Figure 3–4
write cycles, respectively.
Figure 3–4. Cyclone III Device Family Address Clock Enable During Read Cycle Waveform
latched address
(inside memory)
addressstall
q (asynch)
rdaddress
q (synch)
inclock
shows an address clock enable block diagram. The address register output
and
rden
Figure 3–5
doutn-1
doutn
addressstall
an
address[N]
address[0]
a0
clock
doutn
show the address clock enable waveform during read and
a0
dout0
a1
dout0
dout1
a2
Chapter 3: Memory Blocks in the Cyclone III Device Family
address[N]
address[0]
register
register
dout1
a1
dout1
a3
dout1
dout1
© December 2009 Altera Corporation
address[0]
address[N]
a4
dout1
a4
dout4
a5
dout4
a5
dout5
Overview
a6