DSP56301PW80 Freescale Semiconductor, DSP56301PW80 Datasheet - Page 25

• Manufacturer Part Number: DSP56301PW80
• Description: IC DSP 24BIT 80MHZ 208-LQFP
• Manufacturer: Freescale Semiconductor
• Series: DSP563xxr
• Type: Fixed Pointr

Specifications of DSP56301PW80

• Interface: Host Interface, SSI, SCI
• Clock Rate: 80MHz
• Non-volatile Memory: ROM (9 kB)
• On-chip Ram: 24kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 208-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

1.12 JTAG/OnCE Interface
Freescale Semiconductor
TCK
TDI
TDO
TMS
TRST
DE
Signal Name
Input
Input
Output
Input
Input
Input/Output
Type
Tri-stated
Input
Input
Input
Input
Input
State During
Reset
Table 1-16.
DSP56301 Technical Data, Rev. 10
Test Clock
A test clock signal for synchronizing JTAG test logic.
This input is 5 V tolerant.
Test Data Input
A test data serial signal for test instructions and data. TDI is sampled on the
rising edge of TCK and has an internal pull-up resistor.
This input is 5 V tolerant.
Test Data Output
A test data serial signal for test instructions and data. TDO can be tri-stated.
The signal is actively driven in the shift-IR and shift-DR controller states and
changes on the falling edge of TCK.
This input is 5 V tolerant.
Test Mode Select
Sequences the test controller’s state machine, is sampled on the rising edge of
TCK, and has an internal pull-up resistor.
This input is 5 V tolerant.
Test Reset
Asynchronously initializes the test controller, has an internal pull-up resistor,
and must be asserted after power up.
This input is 5 V tolerant.
Debug Event
Provides a way to enter Debug mode from an external command controller (as
input) or to acknowledge that the chip has entered Debug mode (as output).
When asserted as an input, DE causes the DSP56300 core to finish the
current instruction, save the instruction pipeline information, enter Debug
mode, and wait for commands from the debug serial input line. When a debug
request or a breakpoint condition causes the chip to enter Debug mode, DE is
asserted as an output for three clock cycles. DE has an internal pull-up
resistor.
DE is not a standard part of the JTAG Test Access Port (TAP) Controller. It
connects to the OnCE module to initiate Debug mode directly or to provide a
direct external indication that the chip has entered the Debug mode. All other
interface with the OnCE module must occur through the JTAG port.
This input is 5 V tolerant.
JTAG/OnCE Interface
Signal Description
JTAG/OnCE Interface
1-21