DSP56301PW80 Freescale Semiconductor, DSP56301PW80 Datasheet - Page 11
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DSP56301PW80
Manufacturer Part Number
DSP56301PW80
Description
IC DSP 24BIT 80MHZ 208-LQFP
Manufacturer
Freescale Semiconductor
Series
DSP563xxr
Type
Fixed Pointr
Datasheet
1.DSP56301VF100.pdf
(124 pages)
Specifications of DSP56301PW80
Interface
Host Interface, SSI, SCI
Clock Rate
80MHz
Non-volatile Memory
ROM (9 kB)
On-chip Ram
24kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSP56301PW80
Manufacturer:
SLA
Quantity:
6 217
Company:
Part Number:
DSP56301PW80
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1.5.3
Freescale Semiconductor
AA0/RAS0–
AA3/RAS3
RD
WR
TA
BR
BG
Signal Name
External Bus Control
Output
Output
Output
Input
Output
Input
Type
Tri-stated
Tri-stated
Tri-stated
Ignored Input
Output
(deasserted)
Ignored Input
State During
Table 1-8.
Reset
DSP56301 Technical Data, Rev. 10
External Bus Control Signals
Address Attribute or Row Address Strobe
As AA, these signals function as chip selects or additional address lines.
Unlike address lines, however, the AA lines do not hold their state after a read
or write operation. As RAS, these signals can be used for Dynamic Random
Access Memory (DRAM) interface. These signals have programmable
polarity.
Read Enable
When the DSP is the bus master, RD is asserted to read external memory on
the data bus (D[0–23]). Otherwise, RD is tri-stated.
Write Enable
When the DSP is the bus master, WR is asserted to write external memory on
the data bus (D[0–23]). Otherwise, WR is tri-stated.
Transfer Acknowledge
If the DSP56301 is the bus master and there is no external bus activity, or the
DSP56301 is not the bus master, the TA input is ignored. The TA input is a
Data Transfer Acknowledge (DTACK) function that can extend an external bus
cycle indefinitely. Any number of wait states (1, 2,..., infinity) can be added to
the wait states inserted by the BCR by keeping TA deasserted. In typical
operation, TA is deasserted at the start of a bus cycle, asserted to enable
completion of the bus cycle, and deasserted before the next bus cycle. The
current bus cycle completes one clock period after TA is asserted
synchronous to CLKOUT. The number of wait states is determined by the TA
input or by the Bus Control Register (BCR), whichever is longer. The BCR can
set the minimum number of wait states in external bus cycles.
To use the TA functionality, the BCR must be programmed to at least one wait
state. A zero wait state access cannot be extended by TA deassertion;
otherwise improper operation may result. TA can operate synchronously or
asynchronously, depending on the setting of the TAS bit in the Operating
Mode Register (OMR).
TA functionality cannot be used during DRAM-type accesses; otherwise
improper operation may result.
Bus Request
Asserted when the DSP requests bus mastership and deasserted when the
DSP no longer needs the bus. BR can be asserted or deasserted
independently of whether the DSP56301 is a bus master or a bus slave. Bus
“parking” allows BR to be deasserted even though the DSP56301 is the bus
master (see the description of bus “parking” in the BB signal description). The
Bus Request Hole (BRH) bit in the BCR allows BR to be asserted under
software control, even though the DSP does not need the bus. BR is typically
sent to an external bus arbitrator that controls the priority, parking and tenure
of each master on the same external bus. BR is affected only by DSP requests
for the external bus, never for the internal bus. During hardware reset, BR is
deasserted and the arbitration is reset to the bus slave state.
Bus Grant
Must be asserted/deasserted synchronous to CLKOUT for proper operation.
An external bus arbitration circuit asserts BG when the DSP56301 becomes
the next bus master. When BG is asserted, the DSP56301 must wait until BB
is deasserted before taking bus mastership. When BG is deasserted, bus
mastership is typically given up at the end of the current bus cycle. This may
occur in the middle of an instruction that requires more than one external bus
cycle for execution.
Signal Description
External Memory Expansion Port (Port A)
1-7