DSP56301PW80 Freescale Semiconductor, DSP56301PW80 Datasheet - Page 22
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DSP56301PW80
Manufacturer Part Number
DSP56301PW80
Description
IC DSP 24BIT 80MHZ 208-LQFP
Manufacturer
Freescale Semiconductor
Series
DSP563xxr
Type
Fixed Pointr
Datasheet
1.DSP56301VF100.pdf
(124 pages)
Specifications of DSP56301PW80
Interface
Host Interface, SSI, SCI
Clock Rate
80MHz
Non-volatile Memory
ROM (9 kB)
On-chip Ram
24kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
208-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSP56301PW80
Manufacturer:
SLA
Quantity:
6 217
Company:
Part Number:
DSP56301PW80
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Signals/Connections
1.9 Enhanced Synchronous Serial Interface 1 (ESSI1)
1-18
SC10
PD0
SC11
PD1
SC12
PD2
SCK1
PD3
Signal Name
Input or Output
Input/Output
Input or Output
Input/Output
Input or Output
Input/Output
Input or Output
Type
Table 1-13.
Input
Input
Input
Input
State During
Reset
Enhanced Synchronous Serial Interface 1 (ESSI1)
DSP56301 Technical Data, Rev. 10
Serial Control 0
Selection of Synchronous or Asynchronous mode determines function. For
Asynchronous mode, this signal is the receive clock I/O (Schmitt-trigger input).
For Synchronous mode, this signal is either Transmitter 1 output or Serial I/O
Flag 0.
Port D 0
The default configuration following reset is GPIO. For PD0, signal direction is
controlled through the Port Directions Register (PRR1). The signal can be
configured as an ESSI signal SC10 through the Port Control Register (PCR1).
This input is 5 V tolerant.
Serial Control 1
Selection of Synchronous or Asynchronous mode determines function. For
Asynchronous mode, this signal is the receiver frame sync I/O. For
Synchronous mode, this signal is either Transmitter 2 output or Serial I/O Flag
1.
Port D 1
The default configuration following reset is GPIO. For PD1, signal direction is
controlled through PRR1. The signal can be configured as an ESSI signal
SC11 through PCR1.
This input is 5 V tolerant.
Serial Control Signal 2
Frame sync for both the transmitter and receiver in Synchronous mode, for the
transmitter only in Asynchronous mode. When configured as an output, this
signal is the internally generated frame sync signal. When configured as an
input, this signal receives an external frame sync signal for the transmitter (and
the receiver in Synchronous operation).
Port D 2
The default configuration following reset is GPIO. For PD2, signal direction is
controlled through PRR1. The signal can be configured as an ESSI signal
SC12 through PCR1.
This input is 5 V tolerant.
Serial Clock
Provides the serial bit rate clock for the ESSI interface. Clock input or output
can be used by the transmitter and receiver in Synchronous modes, by the
transmitter only in Asynchronous modes.
Although an external serial clock can be independent of and asynchronous to
the DSP system clock, it must exceed the minimum clock cycle time of 6T (that
is, the system clock frequency must be at least three times the external ESSI
clock frequency). The ESSI needs at least three DSP phases inside each half
of the serial clock.
Port D 3
The default configuration following reset is GPIO. For PD3, signal direction is
controlled through PRR1. The signal can be configured as an ESSI signal
SCK1 through PCR1.
This input is 5 V tolerant.
Signal Description
Freescale Semiconductor