DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet - Page 62

IC DSP 24BIT AUD 120MHZ 144-LQFP

DSPB56366AG120

Manufacturer Part Number
DSPB56366AG120
Description
IC DSP 24BIT AUD 120MHZ 144-LQFP
Manufacturer
Freescale Semiconductor
Series
Symphony™r
Type
Audio Processorr
Datasheet

Specifications of DSPB56366AG120

Interface
Host Interface, I²C, SAI, SPI
Clock Rate
120MHz
Non-volatile Memory
ROM (240 kB)
On-chip Ram
69kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 110°C
Mounting Type
Surface Mount
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Background explanation for Asynchronous Bus Arbitration:
The asynchronous bus arbitration is enabled by internal synchronization circuits on BG and BB inputs.
These synchronization circuits add delay from the external signal until it is exposed to internal logic. As a
result of this delay, a 56300 part may assume mastership and assert BB for some time after BG is negated.
This is the reason for timing 250.
Once BB is asserted, there is a synchronization delay from BB assertion to the time this assertion is
exposed to other 56300 components which are potential masters on the same bus. If BG input is asserted
before that time, a situation of BG asserted, and BB negated, may cause another 56300 component to
assume mastership at the same time. Therefore some non-overlap period between one BG input active to
another BG input active is required. Timing 251 ensures that such a situation is avoided.
3-36
BG1
BB
BG2
BG1
BG2
Figure 3-18 Asynchronous Bus Arbitration Timing
Figure 3-19 Asynchronous Bus Arbitration Timing
DSP56366 Technical Data, Rev. 3.1
250+251
250
251
Freescale Semiconductor

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