DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet - Page 10

• Manufacturer Part Number: DSPB56366AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56366AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (240 kB)
• On-chip Ram: 69kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-7 External Bus Control Signals (continued)
State during
Signal Name
Type
Signal Description
Reset
TA
Input
Ignored Input Transfer Acknowledge—If the DSP is the bus master and there is no external
bus activity, or the DSP is not the bus master, the TA input is ignored. The TA
input is a data transfer acknowledge (DTACK) function that can extend an
external bus cycle indefinitely. Any number of wait states (1, 2. . .infinity) may be
added to the wait states inserted by the BCR by keeping TA deasserted. In
typical operation, TA is deasserted at the start of a bus cycle, is asserted to
enable completion of the bus cycle, and is deasserted before the next bus cycle.
The current bus cycle completes one clock period after TA is asserted
synchronous to the internal system clock. The number of wait states is
determined by the TA input or by the bus control register (BCR), whichever is
longer. The BCR can be used to set the minimum number of wait states in
external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at least
one wait state. A zero wait state access cannot be extended by TA deassertion,
otherwise improper operation may result. TA can operate synchronously or
asynchronously, depending on the setting of the TAS bit in the operating mode
register (OMR).
TA functionality may not be used while performing DRAM type accesses,
otherwise improper operation may result.
BR
Output
Output
Bus Request—BR is an active-low output, never tri-stated. BR is asserted
when the DSP requests bus mastership. BR is deasserted when the DSP no
(deasserted)
longer needs the bus. BR may be asserted or deasserted independent of
whether the DSP56366 is a bus master or a bus slave. Bus “parking” allows BR
to be deasserted even though the DSP56366 is the bus master. (See the
description of bus “parking” in the BB signal description.) The bus request hold
(BRH) bit in the BCR allows BR to be asserted under software control even
though the DSP does not need the bus. BR is typically sent to an external bus
arbitrator that controls the priority, parking, and tenure of each master on the
same external bus. BR is only affected by DSP requests for the external bus,
never for the internal bus. During hardware reset, BR is deasserted and the
arbitration is reset to the bus slave state.
DSP56366 Technical Data, Rev. 3.1
2-6
Freescale Semiconductor