DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet - Page 17

• Manufacturer Part Number: DSPB56366AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56366AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (240 kB)
• On-chip Ram: 69kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Signal
HREQ
Name
HA0
HA2
SS
Signal Type
Input or
Output
Input
Input
Input
State during
Tri-stated
Tri-stated
Reset
Table 2-10 Serial Host Interface Signals (continued)
I
the I
the slave device address. HA0 is ignored when configured for the I
This signal is tri-stated during hardware, software, and individual reset. Thus, there
is no need for an external pull-up in this state.
This input is 5 V tolerant.
SPI Slave Select—This signal is an active low Schmitt-trigger input when
configured for the SPI mode. When configured for the SPI Slave mode, this signal
is used to enable the SPI slave for transfer. When configured for the SPI master
mode, this signal should be kept deasserted (pulled high). If it is asserted while
configured as SPI master, a bus error condition is flagged. If SS is deasserted, the
SHI ignores SCK clocks and keeps the MISO output signal in the high-impedance
state.
I
the I
form the slave device address. HA2 is ignored in the I
This signal is tri-stated during hardware, software, and individual reset. Thus, there
is no need for an external pull-up in this state.
This input is 5 V tolerant.
Host Request—This signal is an active low Schmitt-trigger input when configured
for the master mode but an active low output when configured for the slave mode.
When configured for the slave mode, HREQ is asserted to indicate that the SHI is
ready for the next data word transfer and deasserted at the first clock pulse of the
new data word transfer. When configured for the master mode, HREQ is an input.
When asserted by the external slave device, it will trigger the start of the data word
transfer by the master. After finishing the data word transfer, the master will await
the next assertion of HREQ to proceed to the next transfer.
This signal is tri-stated during hardware, software, personal reset, or when the
HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up
in this state.
This input is 5 V tolerant.
2
2
DSP56366 Technical Data, Rev. 3.1
C Slave Address 0—This signal uses a Schmitt-trigger input when configured for
C Slave Address 2—This signal uses a Schmitt-trigger input when configured for
2
2
C mode. When configured for I
C mode. When configured for the I
Signal Description
2
C slave mode, the HA0 signal is used to form
2
C Slave mode, the HA2 signal is used to
2
C master mode.
2
C master mode.
2-13