DSPB56366AG120 Freescale Semiconductor, DSPB56366AG120 Datasheet - Page 22

• Manufacturer Part Number: DSPB56366AG120
• Description: IC DSP 24BIT AUD 120MHZ 144-LQFP
• Manufacturer: Freescale Semiconductor
• Series: Symphony™r
• Type: Audio Processorr

Specifications of DSPB56366AG120

• Interface: Host Interface, I²C, SAI, SPI
• Clock Rate: 120MHz
• Non-volatile Memory: ROM (240 kB)
• On-chip Ram: 69kB
• Voltage - I/o: 3.30V
• Voltage - Core: 3.30V
• Operating Temperature: -40°C ~ 110°C
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.10
2-18
SCKR_1
Signal
FSR_1
FST_1
Name
PE1
PE4
Enhanced Serial Audio Interface_1
Input, output, or
Input, output, or
Input or output
Input or output
Input or output
disconnected
disconnected
Signal Type
Table 2-12 Enhanced Serial Audio Interface_1 Signals
disconnected
disconnected
disconnected
disconnected
disconnected
State during
Reset
GPIO
GPIO
GPIO
GPIO
GPIO
DSP56366 Technical Data, Rev. 3.1
Frame Sync for Receiver_1—This is the receiver frame sync input/output
signal. In the asynchronous mode (SYN=0), the FSR pin operates as the
frame sync input or output used by all the enabled receivers. In the
synchronous mode (SYN=1), it operates as either the serial flag 1 pin
(TEBE=0), or as the transmitter external buffer enable control (TEBE=1,
RFSD=1).
When this pin is configured as serial flag pin, its direction is determined by
the RFSD bit in the RCCR register. When configured as the output flag OF1,
this pin will reflect the value of the OF1 bit in the SAICR register, and the
data in the OF1 bit will show up at the pin synchronized to the frame sync in
normal mode or the slot in network mode. When configured as the input flag
IF1, the data value at the pin will be stored in the IF1 bit in the SAISR
register, synchronized by the frame sync in normal mode or the slot in
network mode.
Port E 1—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input cannot tolerate 5 V.
Frame Sync for Transmitter_1—This is the transmitter frame sync
input/output signal. For synchronous mode, this signal is the frame sync for
both transmitters and receivers. For asynchronous mode, FST is the frame
sync for the transmitters only. The direction is determined by the transmitter
frame sync direction (TFSD) bit in the ESAI transmit clock control register
(TCCR).
Port E 4—When the ESAI is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected.
The default state after reset is GPIO disconnected.
This input cannot tolerate 5 V.
Receiver Serial Clock_1—SCKR provides the receiver serial bit clock for
the ESAI. The SCKR operates as a clock input or output used by all the
enabled receivers in the asynchronous mode (SYN=0), or as serial flag 0 pin
in the synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is determined by
the RCKD bit in the RCCR register. When configured as the output flag OF0,
this pin will reflect the value of the OF0 bit in the SAICR register, and the
data in the OF0 bit will show up at the pin synchronized to the frame sync in
normal mode or the slot in network mode. When configured as the input flag
IF0, the data value at the pin will be stored in the IF0 bit in the SAISR
register, synchronized by the frame sync in normal mode or the slot in
network mode.
Signal Description
Freescale Semiconductor